Static information storage and retrieval – Format or disposition of elements
Reexamination Certificate
2000-07-14
2001-10-16
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Format or disposition of elements
C365S052000, C365S149000
Reexamination Certificate
active
06304478
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to a layout for a semiconductor memory with multiple memory cells.
BACKGROUND OF THE INVENTION
Future microelectronic circuits will use complicated memory architectures with a total in the range of 10
12
to 10
15
transistors. For financial reasons, one elementary boundary condition is no doubt the desire to use the surface area of each of the memory cells optimally and also to obtain the best possible layout of the memory cells on the semiconductor chip. The size of an individual memory cell, the total number of memory cells and also their wiring extent are significant determining factors for defining the overall surface area of the semiconductor memory.
In particular with regard to the wiring, specific design rules must be followed, i.e., defined, specified instructions relating to the minimum spacing of the individual circuit paths and their contacts with each other. In particular, the size of the individual contacts plays a fundamental role since their lateral dimensions are specified as relatively large in comparison to the corresponding circuit paths..
The invention is thus based on the problem of defining a space-saving layout for a semiconductor memory.
SUMMARY OF THE INVENTION
The layout according to this invention takes into account the “design rules” specified by the manufacturing process or those required by the technology, and it attempts to optimize the surface area of the layout of the semiconductor memory. The particular advantage of the invention rests in the fact that for each memory cell, effectively only one contact terminal is needed. In this manner, the required surface area for the semiconductor memory can be reduced significantly. Due to the reduction in the number of contact terminals, the leakage currents can also be reduced.
The invention is particularly valuable for semiconductor memories with so-called dual-port memory cells. In this case, the two bit-line decoders can each be located at opposite sides of the cell field of the semiconductor memory. The different bit lines then lead the particular data signals in opposite directions. Due to this very favorable arrangement of the bit line decoder, the signal-to-noise ratio can be reduced significantly.
The additional claims relate to preferred embodiments and refinements of the invention.
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Chin Dexter K.
Infineon - Technologies AG
Nguyen Tan T.
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