Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Layout editor
Reexamination Certificate
2011-08-16
2011-08-16
Levin, Naum (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Layout editor
C716S119000, C703S014000, C257S204000
Reexamination Certificate
active
08001517
ABSTRACT:
A semiconductor integrated circuit includes multiple cells each containing transistors. The transistors include a gate and diffusion layers. The multiple cells are adjacently formed in a first direction perpendicular to the gate. The distance between the cell border and the adjacent and corresponding diffusion layer, the first direction, is the same.
REFERENCES:
patent: 5051917 (1991-09-01), Gould et al.
patent: 5291043 (1994-03-01), Arakawa
patent: 5612893 (1997-03-01), Hao et al.
patent: 5625568 (1997-04-01), Edwards et al.
patent: 6194252 (2001-02-01), Yamaguchi
patent: 6271548 (2001-08-01), Umemoto et al.
patent: 6385761 (2002-05-01), Breid
patent: 6418551 (2002-07-01), McKay et al.
patent: 6598214 (2003-07-01), Chatterjee et al.
patent: 7032194 (2006-04-01), Hsueh et al.
patent: 7093215 (2006-08-01), Sahara et al.
patent: 7200825 (2007-04-01), Watson et al.
patent: 7222060 (2007-05-01), Shimizu et al.
patent: 7290234 (2007-10-01), Shibayama
patent: 7320116 (2008-01-01), Mukaihira
patent: 7321139 (2008-01-01), Chang et al.
patent: 7484198 (2009-01-01), Lin et al.
patent: 7600207 (2009-10-01), Moroz et al.
patent: 2003/0127697 (2003-07-01), Ohta et al.
patent: 2004/0153986 (2004-08-01), Sahara et al.
patent: 2006/0145266 (2006-07-01), Zushi et al.
patent: 2006/0259881 (2006-11-01), Sahara et al.
patent: 2007/0157144 (2007-07-01), Mai et al.
patent: 2010/0001763 (2010-01-01), Kobayashi
patent: 2004-241529 (2004-08-01), None
patent: 2006-190727 (2006-07-01), None
U.S. Office Action dated Jul. 8, 2010 for U.S. Appl. No. 12/585,183.
Office Action dated Mar. 21, 2011 for U.S. Appl. No. 12/585,183.
Levin Naum
McGinn IP Law Group PLLC
Renesas Electronics Corporation
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