Layout configuration for an integrated circuit gate array

Details Layout configuration for an integrated circuit gate array Layout configuration for an integrated circuit gate array

1995-06-07

1997-08-19

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

257203, 257210, H01L 2710

Patent

active

056591896

ABSTRACT:
A semiconductor device includes a configuration having an array of logic gates electrically connected with an array of input/output (I/O) circuit devices, and also electrically connecting with an array of connector pads by which electrical connection with the semiconductor device may be effected. The array of logic gates is linearly continuous and is unbounded along at least a first axis through to boundaries imposed an edge of the semiconductor wafer. The arrays of I/O circuit devices and connector pads are disposed adjacent, and in one embodiment parallel, to the array of logic gates. Integrated circuit structures including a customized number of individual logic gate elements may be easily provided by cutting a selected length from the strip-like portion of the array of logic gates. Requisite connector pad and I/O circuit features are provided by the adjacent arrays of I/O circuit devices and the adjacent array of connector pads.

REFERENCES:
patent: 4984050 (1991-01-01), Kobayashi
patent: 5109265 (1992-04-01), Utesch et al.
patent: 5440153 (1995-08-01), Male et al.

Affiliated with

Also associated with

Rating

Layout configuration for an integrated circuit gate array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Layout configuration for an integrated circuit gate array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Layout configuration for an integrated circuit gate array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1106884