Layout circuit having a combined tie cell

Details Layout circuit having a combined tie cell Layout circuit having a combined tie cell

2011-05-24

2011-05-24

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Layout editor

C716S119000, C716S120000, C326S027000, C326S104000, C326S122000

Reexamination Certificate

active

07949988

ABSTRACT:
A layout circuit is provided, comprising standard cells, a spare cell, combined tie cells and normal filler cells. The standard cells are disposed and routed on a layout area. The spare cell is added on the layout area and provided for replacing one of the standard cells while adding or changing functions later. The combined tie cells are added on the layout area. The normal filler cells are added on the rest of the layout area. The combined tie cell comprises a tie-high circuit, a tie-low circuit and a capacitance circuit. Some standard cells are disposed near at least one combined tie cell for avoiding routing congestion between the combined tie cells and the replaced standard cell. A circuit layout method is also provided.

REFERENCES:
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patent: 1822347 (2006-08-01), None
English abstract of CN1822347, pub. Aug. 23, 2006.

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