Layout architecture for core I/O buffer

Details Layout architecture for core I/O buffer Layout architecture for core I/O buffer

1998-01-14

2000-09-05

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Integrated structure

364491, 257357, H01L 2500

Patent

active

061149039

ABSTRACT:
An integrated circuit residing within a die includes at least two columns of circuits separated by a routing space. A buffer is formed within the integrated circuit for transferring signals between the integrated circuit and a location remote from the die. At least one portion of the buffer is formed as a buffer circuit column, where the buffer circuit column is aligned with a column of circuits within the integrated circuit but outside of the buffer.

REFERENCES:
patent: 4278897 (1981-07-01), Ohno et al.
patent: 4488267 (1984-12-01), Harrison
patent: 5307286 (1994-04-01), Rusu et al.
patent: 5452251 (1995-09-01), Akaogi et al.
patent: 5663677 (1997-09-01), Freyman et al.
patent: 5694078 (1997-12-01), Nomura et al.
patent: 5744839 (1998-04-01), Ma et al.

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