Layout algorithm for generating power supply interconnections fo

Details Layout algorithm for generating power supply interconnections fo Layout algorithm for generating power supply interconnections fo

1997-07-25

1999-10-26

Booth, Richard

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

364491, 438599, H01L 2182, H01L 2144, G06F 1500

Patent

active

059727403

ABSTRACT:
A method of designing an integrated circuit device having a plurality of arrays of cells on a chip and a plurality of circuit blocks larger in scale than the cells and embedded among the arrays of cells, including the steps of placing the cells and the circuit blocks in a region of a chip, grouping adjacent ones of the circuit blocks, generating a group power supply ring around the grouped circuit blocks and a block power supply ring around another one of the circuit blocks, and generating a grid-shaped pattern of internal power supply interconnections on the chip which are connected to the group power supply ring or the block power supply ring.

REFERENCES:
patent: 5145800 (1992-09-01), Arai et al.
patent: 5493506 (1996-02-01), Kazuhiro et al.
patent: 5666288 (1997-09-01), Jones et al.
patent: 5675501 (1997-10-01), Aoki
patent: 5712793 (1998-01-01), Scepanovic et al.
patent: 5824570 (1998-10-01), Aoki et al.

Affiliated with

Also associated with

Rating

Layout algorithm for generating power supply interconnections fo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Layout algorithm for generating power supply interconnections fo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Layout algorithm for generating power supply interconnections fo will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-763374