Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Patent
1997-08-05
1999-09-28
Talbot, Brian K.
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
4271261, 4273977, 4274197, 4273762, 438225, 438297, 438362, 438439, 438649, 438655, 438664, 438229FOR, B05D 512, H01L 218238
Patent
active
059585056
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The invention relates to a process for producing a layered structure. Furthermore, the invention relates to a layered structure with a silicide layer. Further the invention relates to an electronic component containing such a layered structure. Finally the invention relates to a process for structuring such a layered structure.
BACKGROUND OF THE INVENTION
For numerous applications in the microelectronics field, such layered structures with metallically conductive or semiconductive structures buried especially in silicon are becoming increasingly significant. For realizing such structures, for example of buried interconnects, heretofore there have been no suitable layered structures and processes of manufacture directed to them. A process is known in the state of the art in which the significant steps are lithographic structuring and etching of troughs in silicon, optionally selective deposition of a metal, the filling of the troughs with, for example, SiO.sub.2 and the removal of deposited materials can be mentioned.
This process is very expensive and, above all, is exceptionally problematical for submicron structuring magnitudes. Furthermore, in this process the danger of contamination of the metal/silicon boundary layer by undesired edge coverings is unavoidable. The production of epitactic layers is not possible therewith.
In the field of microelectronics, from "Silicides and Contacts for ULSI" in Handbook of Multilevel Metallization for Integrated Circuits, published by S. R. Wilson and C. J. Tracy, Noyes Publications, P. 32-96, 1993, two silicides, TiSi.sub.2 and CoSi.sub.2 have been described as state of the art, especially for the metallization of the source, gate and drain of metal oxide field effect transistors (MOSFET). Both suicides permit a self-adjusting process in the course of silicide formation and are characterized by a low electrical resistance of about 15 .mu.ohm cm. Flat p.sup.+
transitions with epitactic CoSi.sub.2 layers are advantageous in comparison to polycrystalline metallization. From Appl. Phys. Lett. 58, P. 1308-1310, 1991, it is known to produce monocrystalline CoSi.sub.2 layers with the so-called TiCo process by sputter deposition and heat treatment. Monocrystalline CoSi.sub.2 layers are characterized, by contrast with polycrystalline silicides by a significantly higher thermal stability: monocrystalline CoSi.sub.2 layers, especially as they are buried in silicon, are stable to about 1200.degree. C.
However, the hitherto known processes are precisely not suitable for the production of layered structures of the silicides since contamination and also a qualitatively insufficient passivation are problems which cannot be overcome.
OBJECTS OF THE INVENTION
It is therefore an object of the invention to obtain a layered structure of the originally described type which enables its use for the production of components in the field of silicon technology and which eliminates or significantly reduces the drawbacks arising in the state of the art. It is a further object of the invention to provide a method of producing such layered structures that these drawbacks are not manifest.
A further object of the invention is to obtain a component containing such a layered structure as can be employed in silicon technology.
SUMMARY OF THE INVENTION
These objects are attained, in accordance with the invention with a layered structure and a method or process for making same, in which a silicide layer is provided on a silicon-containing surface, e.g. a silicon substrate and the silicide layer is subjected to local oxidation to cause that silicide layer to grow into the silicon substrate.
It has been recognized that with local oxidation of the silicide layer from its boundary surface into the interior, the silicide layer can be oxidized to SiO.sub.2. It is however also been recognized that simultaneously on the surface opposite this silicide boundary layer and connected with the silicon-containing surface or substrate surface the silicide during local oxidation grow
REFERENCES:
patent: 4971655 (1990-11-01), Stefano et al.
patent: 5624871 (1997-04-01), Teo et al.
patent: 5635426 (1997-06-01), Hayashi et al.
Miyao et al., "Characterization and application of fine-patterned Si/CoSi2/Si double heterostructures fabricted by self-aligned, two step MBE", Journal of Crystal Growth, vol. 111, May 1991.
IBM Technical Disclosure, "Interconnect Fabrication by local metal oxidation", Jul. 1991.
Dass et al., "Growth of epitaxial CoSi2 on (100) Si", Applied Physics Letters, vol. 58, Mar. 1991.
IBM Technical Disclosure Bulletin, "Pattering and etching of silicde layers", vol. 33, No. 10a, Mar. 1991.
Handbook of Multilevel Metallization for Integrated Circuits, by Wilson et al., pp. 32-96 no month available.
"Growth of epitaxial CoSi.sub.2 on (100) Si" by Dass et al., Appl. Phys. Lett. 58 (12) Mar. 25, 1991.
"Patterning method for silicides based on local oxidatiob" by S. Mantl et al., Appl. Phys. Lett. 67 (23) Dec. 4, 1995.
Thermal Oxidation of Transition Metal Silicides by H. Jiang et al. (2194 Thin Solid Films, 140 (1986) Jun. 16, No. 1).
"Characterizetion and appliction of fine-patterned Si/CoSi.sub.2 /Si double heterostructures . . . " by Miyao et al., 2300 Journal of Crystal Growth 111 (1991)May II Nos. 1/4.
"Use of TiSi.sub.2 to form metal-oxide-silicon field effect transistors . . ." by T. Yachi et al. (J. Vac.Sci. Technol. B 3(4), Jul./Aug. 1985.
Enhanced Oxidation of CVD Tungsten Silicide Films by Yanai et al. (1046B Extended Abstracts 86-1(1986) May No. 1.
Interconnect Fabrication by Local Metal Oxidation (IBM Technical Disclosure Bulletin vol. 34, No. 2 Jul. 1991).
Patterning and Etching of Silicide Layers (IBM Technical Disclosure Bulletin Vo. 33 No. 10A Mar. 1991).
Silicon Processing for the VLSI Era, vol. 2, Process Integration Mesotaxy: Single-crystal growth of buried CoSi.sub.2 layers, pub. Nov. 11, 1986.
Dubno Herbert
Forschungszentrum Julich GmbH
Talbot Brian K.
LandOfFree
Layered structure with a silicide layer and process for producin does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Layered structure with a silicide layer and process for producin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Layered structure with a silicide layer and process for producin will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-700690