Layered local interconnect compatible with integrated circuit fe

Details Layered local interconnect compatible with integrated circuit fe Layered local interconnect compatible with integrated circuit fe

1994-08-22

1996-03-12

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437245, 437246, 437 52, H01L 2144

Patent

active

054985692

ABSTRACT:
A method of forming a local interconnect for a ferroelectric memory cell includes the steps of simultaneously opening top electrode and source/drain contacts to the ferroelectric memory cell, sputtering a first blanket metal layer comprised of platinum or palladium on a top surface of the ferroelectric memory cell, annealing the ferroelectric memory cell to simultaneously recover damage in a ferroelectric capacitor dielectric of the memory cell, and to silicidize the first metal layer in the source/drain contact, sputtering a second blanket metal layer comprised of titanium nitride on a top surface of the first metal layer, and selectively etching the first and second metal layers to form the local interconnect between the top electrode and source/drain contacts of the ferroelectric memory cell.

REFERENCES:
patent: 5320971 (1994-06-01), Eklund et al.
patent: 5374578 (1994-12-01), Patel et al.
Hayashida, et al. "Manufactuable Local Interconnect Technology Fully Compatible With Titanium Salicide Process." Jun. 11-12, 1991. VMIC Conference. pp. 332-334.

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