Layered features for co-fired module integration

Details Layered features for co-fired module integration Layered features for co-fired module integration

1994-08-26

1996-03-12

Hajec, Donald T.

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257727, 174253, 361783, H01L 2332, H05K 114

Patent

active

054989051

ABSTRACT:
A unitized multilayer circuit structure that includes a plurality of planar dielectric insulating layers stacked in laminar fashion to form a substrate having sides formed by edges of the dielectric insulating layers and recessed regions formed in one or more one sides of the substrate for use in attaching the unitized multilayer circuit structure to a higher level assembly or for attaching electrical contact circuitry to the unitized multilayer circuit structure.

REFERENCES:
patent: 4879588 (1989-11-01), Ohtsuka et al.
patent: 4882657 (1989-11-01), Braun
patent: 5051869 (1991-09-01), Goldfarb
patent: 5136471 (1992-08-01), Inasaka
patent: 5245216 (1993-09-01), Sako
patent: 5303119 (1994-04-01), Hilbrink
patent: 5397916 (1995-03-01), Normington
patent: 5399898 (1995-03-01), Rostoker

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