Layered electronic assembly having compensation for chips of dif

Details Layered electronic assembly having compensation for chips of dif Layered electronic assembly having compensation for chips of dif

1989-08-16

1990-09-25

Thompson, Gregory D.

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

357 79, 361380, 361393, 361417, H05K 700

Patent

active

049597493

ABSTRACT:
A layered electronic assembly contains a plurality of integrated circuit chips that are arranged in a stack; respective adhesive layers interleave the chips and hold them together; and I/O leads on the chips extend to one face of the stack. Also, the chips in the stack have respective thicknesses which vary from chip to chip; the I/O leads are offset from one edge of the chip on which they lie by respective distances which vary from chip to chip; the adhesive layers in the stack have respective thicknesses which compensate for the thickness variations in the chips such that the I/O leads on adjacent chips are spaced by predetermined distances along the stack face; and the chips are shifted relative to one another such that their one edge is misaligned while their I/O leads are aligned on the stack face. This layered electronic assembly uses 100% of the electrically functional chips which are cut from a semiconductor wafer without sacrificing any accuracy with which the I/O leads are aligned on the stack face.

REFERENCES:
patent: 4617160 (1986-10-01), Belanger et al.
patent: 4704319 (1987-11-01), Belanger et al.
patent: 4706166 (1987-11-01), Go

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