Layered dielectric film structure suitable for gate...

Details Layered dielectric film structure suitable for gate... Layered dielectric film structure suitable for gate...

1999-06-17

2002-07-09

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S411000

Reexamination Certificate

active

06417570

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to semiconductor integrated circuit devices most generally, and the processes for forming these devices. More specifically, this invention relates to a layered gate dielectric film structure including a structurally sound plasma nitride film which suppresses boron penetration from a p
+
doped polysilicon structure through gate areas and into channel areas.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuit devices include a thin dielectric material, commonly a thermally grown oxide, which functions as a gate dielectric for transistors incorporated into semiconductor integrated circuit devices. The gate dielectric material is typically formed on a semiconductor substrate over a region which will serve as a channel region. The transistors function when a channel is formed in the semiconductor substrate beneath the gate dielectric in response to a voltage being applied to a gate electrode formed atop the gate dielectric film. The quality and integrity of the gate dielectric film is critical to the functionality and lifetime of the transistor devices, which include a very tightly defined set of operational characteristics which are very sensitive to the materials and methods used to form the transistor devices. It is important, therefore, to suppress the migration of any undesired dopant species into the gate dielectric film, or through the gate dielectric film and into the subjacent channel region.
Polycrystalline silicon films are commonly used as gate electrode materials for transistors in semiconductor integrated circuits. Polycrystalline silicon may be “n-type” polycrystalline silicon or “p-type” polycrystalline silicon. By “p-type” polysilicon material, it is meant that a p-type dopant impurity is introduced into the polycrystalline silicon film. A commonly used, and preferred p-type dopant within the semiconductor industry is boron. When boron is used as an impurity dopant within a polycrystalline silicon film, it is of critical significance to maintain the boron within the polycrystalline silicon film, and especially to suppress migration of the boron into or through the gate dielectric film which forms part of the transistor.
In addition to boron diffusing into the gate dielectric material, the boron can further diffuse through the gate dielectric material and into the channel region of the transistor formed below the gate dielectric region. When boron diffuses into the gate dielectric or the channel region, gate dielectric reliability is degraded and device functionality can be destroyed. It is thus of increased significance to suppress the diffusion of boron from the polysilicon interconnect and gate structures and into and through the gate dielectric films. Boron diffusion occurs during activation processes which utilize temperatures in the range of 1000° C. to 1050° C. to activate the Boron, and also during the operation of the completed device. It is therefore desirable to have a built-in means within the gate electrode/gate dielectric structure which will suppress boron diffusion out of p-type polycrystalline silicon and into or through the gate dielectric material.
One approach to suppressing boron diffusion as above, is to utilize a layered gate dielectric film which includes both an oxide film and a nitride film. An alternate, but similar approach utilizes an oxide film, a nitride film, and a second oxide film. The combination of an oxide and a completely formed nitride film to form a gate dielectric may successfully suppress boron penetration from p-type polysilicon into the underlying channel region. In addition, the combination of an oxide and a nitride film to form a gate dielectric also reduces current leakage. However, gate structures which include a silicon nitride layer typically introduce charge trapping problems and channel mobility degradation, as well as drive current reduction. Charge trapping problems lead to hot carrier aging effects. Additionally, structurally formed silicon nitride films exert a high film stress on the substrate upon which they are formed. This is quite undesirable and can produce dislocations in the crystal lattice which forms the semiconductor substrate, which lead to drive current reduction and junction leakage.
In today's rapidly advancing semiconductor device manufacturing industry, features of the components which form semiconductor integrated circuits, continue to shrink. Consistent with this trend, transistors of increasingly smaller dimensions are being produced. Accordingly, thinner gate dielectric films are necessary. In order to maintain desired electrical operational characteristics of these transistors, a silicon nitride film on the order of 10-50 angstroms would be required for use as part of the layered gate dielectric structures referred to above.
Using currently available methods for forming a structurally correct silicon nitride film, it is difficult to produce such a film having a thickness on the order of 10-50 angstroms. When a nitride film having a thickness within this range is produced according to conventional methods, the film may include pinholes, or small voids. As such, some transistors may have a gate dielectric including pinholes while others may be pinhole-free. Pinholes cause current leakage when a transistor having pinholes is biased using a voltage calculated for a transistor having a pinhole-free nitride film. In addition to pinholes, silicon nitride films formed using currently available methods, include trap sites which can trap charges and degrade the integrity of the film. These trap sites cannot be annealed out using conventional processing technology.
FIG. 2
is a cross-sectional view showing the shortcomings of conventional attempts to introduce a structurally sound silicon nitride film over the gate oxide film to form a layered gate dielectric structure. Conventional silicon nitride film
10
is formed on top surface
6
of oxide film
5
using conventional methods such as chemical vapor deposition (CVD) means, or other furnace operations as standard in the semiconductor processing industry. Using conventional means for forming the silicon nitride film
10
on the substrate, the formed silicon nitride film
10
is a structurally sound silicon nitride film. By structurally sound, it is meant that the silicon nitride film is formed according to the proper stoichiometric ratio of silicon and nitrogen. That is, three atoms of silicon and four atoms of nitrogen combine to form a silicon nitride film represented by the formula Si
3
N
4
. In order to meet the challenging demands of today's semiconductor processing industry, the thickness
11
of silicon nitride film
10
will desirably be on the order of 10 to 50 angstroms in order to accommodate the electrical characteristics sought to be achieved in the transistors which will use this layered gate dielectric structure.
When silicon nitride film
10
is formed using conventional methods, a high film stress is exerted by the deposited film upon the substrate. High film stress exerted on substrates such as silicon wafers commonly used in the semiconductor manufacturing industry, can result in dislocations in the substrate, which lead to drive current reduction and junction leakage. Additionally, conventionally formed silicon nitride film
10
introduces charge trapping problems, as well as mobility and drive current problems.
Moreover, when the thickness
11
of a silicon nitride film
10
formed using conventional methods is less than 50 angstroms, pinholes
13
invariably occur within the silicon nitride film
10
. When these pinholes
13
are produced over channel region
4
and within gate area
7
, the electrical characteristics and reliability of the transistors subsequently formed in gate area
7
, will be compromised. Generally speaking, a high leakage will occur within the transistor, as the transistor will be biased based upon the assumption that silicon nitride film
10
is present and continuous within gate region
7
. When the transistor device is biased acco

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