Layered chip package and method of manufacturing same

Details Layered chip package and method of manufacturing same Layered chip package and method of manufacturing same

2011-01-11

2011-01-11

Clark, S. V (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S777000

Reexamination Certificate

active

07868442

ABSTRACT:
A layered chip package includes a plurality of layer portions stacked, each layer portion including a semiconductor chip having a first surface with a device formed thereon and a second surface opposite thereto. The plurality of layer portions include at least a pair of layer portions disposed such that the first surfaces of the respective semiconductor chips face toward each other. A manufacturing method for the layered chip package includes the steps of: fabricating a layered substructure by stacking a plurality of substructures each including a plurality of layer portions corresponding to the plurality of layer portions of the layered chip package; and fabricating a plurality of layered chip packages by using the layered substructure. The step of fabricating the layered substructure includes: fabricating a first and a second pre-polishing substructure each having a first surface and a second surface; bonding the pre-polishing substructures to each other such that their respective first surfaces face toward each other; and forming a first and a second substructure by polishing the second surfaces.

REFERENCES:
patent: 5571754 (1996-11-01), Bertin et al.
patent: 5648684 (1997-07-01), Bertin et al.
patent: 5656553 (1997-08-01), Leas et al.
patent: 5688721 (1997-11-01), Johnson
patent: 5691248 (1997-11-01), Cronin et al.
patent: 5872025 (1999-02-01), Cronin et al.
patent: 5925924 (1999-07-01), Cronin et al.
patent: 5952725 (1999-09-01), Ball
patent: 5953588 (1999-09-01), Camien et al.
patent: 6355976 (2002-03-01), Faris
patent: 6472746 (2002-10-01), Taniguchi et al.
patent: 6582992 (2003-06-01), Poo et al.
patent: 6706546 (2004-03-01), Yoshimura et al.
patent: 6936913 (2005-08-01), Akerling et al.
patent: 7064444 (2006-06-01), Lee et al.
patent: 7119428 (2006-10-01), Tanie et al.
patent: 7127807 (2006-10-01), Yamaguchi et al.
patent: 7491288 (2009-02-01), Furui et al.
patent: 7572673 (2009-08-01), Chung et al.
patent: 7676912 (2010-03-01), Sasaki et al.
patent: 2002/0096760 (2002-07-01), Simelgor et al.
patent: 2003/0146012 (2003-08-01), Song et al.
patent: 2005/0023656 (2005-02-01), Leedy
patent: 2006/0118972 (2006-06-01), Baek et al.
patent: 2007/0170573 (2007-07-01), Kuroda et al.
patent: 2007/0275505 (2007-11-01), Wolterink et al.
patent: 2008/0006921 (2008-01-01), Park et al.
patent: 2008/0029868 (2008-02-01), Lee et al.
patent: 2008/0083976 (2008-04-01), Haba et al.
patent: 2008/0083977 (2008-04-01), Haba et al.
patent: 2008/0128882 (2008-06-01), Baek et al.
patent: 2008/0230922 (2008-09-01), Mochizuki et al.
patent: 2008/0308946 (2008-12-01), Pratt
patent: 2009/0001600 (2009-01-01), Somani
patent: 2009/0004777 (2009-01-01), Kolan et al.
patent: 2009/0051046 (2009-02-01), Yamazaki et al.
patent: 2009/0115042 (2009-05-01), Koyanagi
patent: 2009/0236031 (2009-09-01), Sunohara et al.
patent: 2009/0305502 (2009-12-01), Lee et al.
patent: 2009/0321957 (2009-12-01), Sasaki et al.
patent: 2009/0325345 (2009-12-01), Sasaki et al.
patent: 2010/0140771 (2010-06-01), Huang et al.
patent: 2010/0230795 (2010-09-01), Kriman et al.
patent: 2010/0240174 (2010-09-01), Yu et al.
Keith D. Gann; “Neo-Stacking Technology,” HDI Mazazine; Dec. 1999.
U.S. Appl. No. 11/878,282, filed Jul. 23, 2007; In the name of Yoshitaka Sasaki et al.
U.S. Appl. No. 11/896,709, filed Sep. 5, 2007; In the name of Yoshitaka Sasaki et al.
U.S. Appl. No. 12/213,645, filed Jun. 23, 2008; In the name of Yoshitaka Sasaki et al.
U.S. Appl. No. 12/216,144, filed Jun. 30, 2008; In the name of Yoshitaka Sasaki et al.
U.S. Appl. No. 12/216,168, filed Jun. 30, 2008; In the name of Yoshitaka Sasaki et al.
Mar. 24, 2010 Notice of Allowance issued in U.S. Appl. No. 12/216,144.
Aug. 17, 2009 Office Action issued in U.S. Appl. No. 12/216,144.
May 20, 2010 Office Action issued in U.S. Appl. No. 12/213,645.
Mar. 29, 2010 Restriction Requirement issued in U.S. Appl. No. 12/213,645.
Jun. 25, 2009 Office Action issued in U.S. Appl. No. 12/216,168.
Jan. 11, 2010 Notice of Allowance issued in U.S. Appl. No. 12/216,168.
Sep. 8, 2010 Notice of Allowance issued in U.S. Pat. Appl. No. 12/213,645.
Oct. 8, 2010 Notice of Allowance issued in U.S. Pat. Appl. No. 12/805,446.

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