Layered capacitor device

Details Layered capacitor device Layered capacitor device

2000-04-07

2001-01-23

Kincaid, Kristina (Department: 2831)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S301400, C361S306300, C361S321200, C257S532000, C257S540000

Reexamination Certificate

active

06178083

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a layered capacitor device and an integrated circuit comprising such a capacitor device.
Such a layered capacitor device is already known in the art, e.g. from the U.S. Pat. No. 4,656,557, entitled ‘
Electrical Layer Capacitor and Method for the Manufacture Thereof’
. Therein, a layered capacitor device is described that is formed by an alternating superposition of electrically conducting layers, called metal coatings in the cited U.S. Patent, and electrically insulating layers, called plastic films in the cited U.S. Patent. In this way, a longitudinal stack of individual capacitors is constructed. Metal coatings of a same polarisation are interconnected so that the individual capacitors become parallel coupled. In case a layered capacitor which forms part of an integrated circuit is given the structure known from U.S. Pat. No. 4,656,557 by alternating superposition of metal layers and oxide layers, the realised capacitance per unit chip area is small.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a layered capacitor device similar to the known one but through which the realised capacitance per unit area increases significantly.
According to the invention, this object is achieved by a layered capacitor device comprising the parallel coupling of a plurality of capacitors constituted by vertically alternating first and second layers, the second layers consisting of electrically insulating material, wherein the first layers consist of horizontally alternating electrically conducting tracks and electrically insulating tracks, whereby top-bottom capacitors are constituted by two vertically neighboring electrically conducting tracks and a second layer of said second layers therebetween, and whereby side-wall capacitors are constituted by two horizontally neighboring said electrically conducting tracks and an electrically insulating track of said electrically insulating tracks therebetween, said top-bottom capacitors and said side-wall capacitors constituting said plurality of capacitors.
In this way, the realised capacitance is the superposition of vertically oriented or top-bottom capacitors and horizontally oriented or side-wall capacitors. The latter side-wall capacitors are bigger than the top-bottom capacitors because the spacing between horizontally neighbouring metal tracks typically is smaller than the spacing between vertically neighbouring metal tracks as a result of the thickness of the insulating layers. Moreover, fringing electrical fields between side-walls of a metal track and top or bottom plates of other metal tracks also have an increasing effect on the realised capacitance per unit area.
It is to be noticed that the term ‘comprising’, used in the claims, should not be interpreted as being limitative to the means listed thereafter. Thus, the scope of the expression ‘a device comprising means A and B’ should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B.
An additional feature of the layered capacitor device according to the present invention is defined by claim
2
.
In this way, by electrically interconnecting all diagonally neighbouring metal tracks, all top-bottom capacitors and all side-wall capacitors become parallel coupled between two contact points of the capacitor device. If the metal tracks are supposed to be labelled with a row index and column index in accordance with their position in the capacitor device, the first contact point is electrically connected to all metal tracks whose row index and column index, when added together, constitute an odd number and the second contact point is electrically connected to all metal tracks whose row index and column index, when added together, constitute an even number.
As described by claim
3
, a capacitor device with a structure according to the present invention is suitable for integration in an integrated circuit, because the area occupied by the integrated circuit is reduced significantly in comparison with an integrated circuit wherein the same aggregate capacitance is realised via a capacitor device with the known structure.


REFERENCES:
patent: 4424552 (1984-01-01), Saint Marcoux
patent: 5168433 (1992-12-01), Mukouyama et al.
patent: 5745335 (1998-04-01), Watt
patent: 5874757 (1999-02-01), Chao
patent: 5978206 (1999-11-01), Nishimura et al.
patent: 6031711 (2000-02-01), Tennent et al.

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