Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
1998-10-30
2001-01-09
Loke, Steven H. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S686000, C257S685000, C257S784000, C257S779000, C257S711000, C257S723000, C257S737000, C257S692000, C438S109000, C438S108000, C438S106000
Reexamination Certificate
active
06172423
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package, and in particular to a ball grid array semiconductor package and a fabrication method thereof.
2. Background of the Related Art
A quad flat package (QFP) is a widely used multipin semiconductor package. However, as a semiconductor package is required to have more pins, a QFP has problems because a lead is easily bent when a width of an outlead becomes narrower and a pitch between leads becomes finer. Further, it is difficult to array a printed circuit board (PCB) and the QFP package while controlling quantity of solder when mounting the package on the PCB. Accordingly, ball grid array (BGA) semiconductor packages, which contain multiple pins and solve the above problems, are being used. The BGA semiconductor package has no outlead because solder balls serve as the outlead, which solves the defects of the QFP.
FIG. 1
is a diagram showing a vertical cross-section of a related art BGA semiconductor package. As shown therein, the related art BGA semiconductor package includes a substrate
1
in which a plurality of patterned conductive lines (not shown) are installed, a semiconductor chip
2
attached on an upper surface of the substrate
1
by an adhesive
3
, a plurality of conductive wires
4
electrically connecting the semiconductor chip
2
and one end of each of the patterned conductive lines installed in the substrate
1
, a molding part
5
and a plurality of solder balls
6
. The molding part
5
formed on the upper surface of the substrate
1
seals the semiconductor chip
2
and the conductive wires
4
. The plurality of solder balls
6
are fixed to a lower surface of the substrate
1
in order to be connected with the other ends of the patterned conductive lines installed in the substrate
1
. Each of the patterned conductive lines becomes an electric channel for connecting the upper and lower parts of the substrate.
However, since the related BGA semiconductor package shown in
FIG. 1
has the solder balls, which become input and output terminals of an electric signal, only on the lower surface thereof, it is difficult or impossible to manufacture a package module with multiple layers of semiconductor packages. Accordingly, it is difficult to expand functional capacities and capabilities in a limited area by layering plural semiconductor packages.
SUMMARY OF THE INVENTION
An object of the present invention to provide a layer-type ball grid array (BGA) semiconductor package and a fabrication method thereof that substantially obviates at least one of the above-described problems of the related art.
Another object of the present invention to provide a layer-type ball grid array (BGA) semiconductor package and a fabrication method thereof that permits layering multiple semiconductor packages.
Another object of the present invention to provide a layer-type ball grid array (BGA) semiconductor package and a fabrication method thereof that expands BGA semiconductor capacity and capability in a limited area.
Another object of the present invention to provide a layer-type ball grid array (BGA) semiconductor package and a fabrication method thereof that electrically couples opposing surfaces of a substrate via an external surface of the substrate.
Another object of the present invention to provide a multiple-layer ball grid array (BGA) semiconductor package and a fabrication method thereof that permits layering semiconductor packages using only a reflow soldering process.
To achieve at least the above objects in a whole or in parts, there is provided a BGA semiconductor package according to the present invention that includes a substrate having a cavity in an upper surface; an interconnection layer having a plurality of conductive interconnections forming electric channels between the upper surface and a lower surface of the substrate wherein the interconnection layer is attached to an external surface of the substrate and extends from the upper surface to the lower surface; a semiconductor chip placed on a bottom of the cavity; a plurality of conductive wires electrically coupling the semiconductor chip to each conductive interconnection; a molding part in the cavity to seal the semiconductor chip and the wires, and a plurality of solder balls correspondingly attached to the conductive interconnections of the interconnection layer on the lower surface of the substrate.
To further achieve the above objects in a whole or in parts, there is provided a BGA semiconductor package fabrication method according to the present invention that includes providing a substrate having upper and lower surfaces; forming a cavity in a part of the upper surface of the substrate; attaching an interconnection pattern layer having a plurality of patterned conductive interconnections that extends from the upper surface to the lower surface of the substrate except in the cavity; attaching a semiconductor chip to a bottom of the cavity; electrically coupling the semiconductor chip to first ends of the corresponding conductive interconnections by a plurality of conductive media; forming a molding part that packages the semiconductor chip and the wires; and attaching a plurality of solder balls to second ends of the conductive interconnections on the lower surface of the substrate.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
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patent: 5838060 (1998-11-01), Comer
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Loke Steven H.
Thai Luan
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