Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
2006-06-13
2006-06-13
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S459000, C438S464000
Reexamination Certificate
active
07060590
ABSTRACT:
The invention relates to a method of removing a peripheral zone of adhesive while using a layer of adhesive in the process of assembling and transferring a layer of material from a source substrate to a support substrate. The method is remarkable in that it includes bonding the two substrates together by means of a curable adhesive so that an excess of adhesive is present. This assures proper bonding and provides a peripheral zone of adhesive outside of the joined substrates. Only that portion of adhesive is cured which is present in a connection zone between the substrates, and the peripheral zone of non-cured adhesive is removed prior to detaching the transferable layer. The invention is applicable to fabricating a composite substrate in the fields of electronics, opto-electronics, or optics.
REFERENCES:
patent: 5374564 (1994-12-01), Bruel
patent: 5391257 (1995-02-01), Sullivan et al.
patent: 5863830 (1999-01-01), Bruel et al.
patent: 6177359 (2001-01-01), Chen et al.
patent: 6287891 (2001-09-01), Sayyah
patent: 6316333 (2001-11-01), Bruel et al.
patent: 6335258 (2002-01-01), Aspar et al.
patent: 6376332 (2002-04-01), Yanagita et al.
patent: 6406636 (2002-06-01), Vaganov
patent: 6448155 (2002-09-01), Iwasaki et al.
patent: 6465327 (2002-10-01), Aspar et al.
patent: 6534380 (2003-03-01), Yamauchi et al.
patent: 6534382 (2003-03-01), Sakaguchi et al.
patent: 6548338 (2003-04-01), Bernstein et al.
patent: 6562648 (2003-05-01), Wong et al.
patent: 6673694 (2004-01-01), Borenstein
patent: 6700631 (2004-03-01), Inoue et al.
patent: 6727549 (2004-04-01), Doyke
patent: 6767763 (2004-07-01), Uchiyama
patent: 6809009 (2004-10-01), Aspar et al.
patent: 2001/0055854 (2001-12-01), Nishida et al.
patent: 2002/0042189 (2002-04-01), Tanaka
patent: 2002/0081822 (2002-06-01), Yanagita et al.
patent: 2002/0096717 (2002-07-01), Chu et al.
patent: 2002/0132451 (2002-09-01), Akino et al.
patent: 2003/0234075 (2003-12-01), Aspar et al.
patent: 0 106 566 (1989-11-01), None
patent: 0 977 252 (2000-02-01), None
patent: 1 059 663 (2000-12-01), None
patent: 2 811 807 (2002-01-01), None
patent: 62229849 (1987-10-01), None
patent: 3106052 (1991-05-01), None
patent: 10320851 (1998-12-01), None
patent: WO 01/04933 (2001-01-01), None
patent: WO 02/05344 (2002-01-01), None
patent: WO 03/081664 (2003-10-01), None
S. Kodama et al., XP-00035156 “Variable Threshold A1GaAs/InGaAs Heterostructure Field-Effect Transistors with Paired Gated Gabricated Using the Wafer-Bonding Technique”, vol. 241ga, p. 434-435 (1999).
Aspar Bernard
Bressot Séverine
Rayssac Olivier
Commissariat à l'Energie Atomique (CEA)
Fourson George
S.O.I. Tec Silicon on Insulator Technologies S.A.
Toledo Fernando L.
Winston & Strawn LLP
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