Layer thin film wiring process featuring self-alignment of vias

Details Layer thin film wiring process featuring self-alignment of vias Layer thin film wiring process featuring self-alignment of vias

1992-04-21

1993-06-15

Zimmerman, John

Stock material or miscellaneous articles

All metal or with adjacent metals

Composite; i.e., plural, adjacent, spatially distinct metal...

428901, 174262, 174264, H05K 102

Patent

active

052196690

ABSTRACT:
The present invention provides a packaging semiconductor structure and method for obtaining same. The structure is comprised of at least one level of dielectric and metallurgy layers. The at least one level is comprised of a wiring metallurgy plane and a "through-via" plane of interconnecting metallurgy in association with both one and two layers of polymeric dielectric materials. The self-alignment method of fabrication of the level provides a streamlined technique wherein stringent masking and alignment requirements are relaxed, undue processing such as at least one polishing step is eliminated and a structure having adhesive integrity is fabricated.

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IBM Technical Disclosure Bulletin, vol. 14, No. 1, Jun. 1971, A. P. David et al., "Producing Integral Via and Pad Metallurgy", p. 101.
IBM Technical Disclosure Bulletin, vol. 19, No. 3, 1976, by S. E. Greer, pp. 911-912.
Ohsaki, et al., "A Fine-Line Multilayer Substrate with Photo-sensitive Polymide Dielectric and Electroless Copper Plated Conductors", Third IEEE/CHMT International Electronic Manufacturing Technology Symposium, pp. 178-183, Oct. 12-, 1987.

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