Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1999-05-20
2001-08-07
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
With measuring or testing
C451S006000, C451S008000, C451S041000, C451S059000, C438S016000
Reexamination Certificate
active
06271047
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to any of various methods for planarizing a surface of a workpiece such as a semiconductor wafer during manufacturing semiconductor devices on the wafer. A representative such method is “chemical mechanical polishing” (“CMP”) as used to planarize semiconductor wafers between certain manufacturing steps. More specifically, the invention pertains to methods and apparatus for detecting a “process endpoint” (i.e., time to stop planarizing).
BACKGROUND OF THE INVENTION
Semiconductor devices (e.g., integrated circuits, displays, and the like) are becoming increasingly dense and highly integrated. With this trend, certain processes such as processes directed to formation of multiple wiring layers, formation of insulating films between wiring layers, formation of inter-layer connecting plugs and the like, and formation of electrodes are becoming increasingly more critical. For example, controlling the thickness and depth profiles of inter-layer insulating films or metal layers is now very important to ensure attainment of target integration levels in devices with high reliability. Achieving such control requires that layer thicknesses in steps such as layer-formation steps and etching steps be monitored.
Responsive to the need to achieve ever-increasing device density along with ever-decreasing feature sizes, the microlithography industry has developed microlithography apparatus that utilize extremely short wavelengths of light, such as deep-UV light, but at large numerical apertures. Projection optics used in such apparatus have extremely short focal ranges. The focal ranges are now so short that the uneven surface that results from stacking multiple layers atop one another during manufacture of an integrated circuit is no longer in sharp focus from peaks to valleys of the surface. Consequently, it has become increasingly important to planarize the surface of the wafer (at least within exposure areas) accurately between certain layer-formation steps. It is also important to perform a planarization step after embedding an inlay of a metal electrode layer to form inter-layer connecting plugs and the like.
Planarization typically involves the removal of material from the surface of the wafer. Whereas several candidate techniques have now been developed for performing planarization, as summarized below, a key problem has been how to accurately detect, during planarization, when to stop planarizing so as to ensure the desired amount of material has been removed without removing excessive material.
Among the several conventional planarization methods, a polishing process termed “chemical mechanical polishing” or “chemical mechanical planarization” (abbreviated “CMP”) has received considerable favor. This is because, inter alia, CMP is effective for planarizing wafers having a large surface area and is effective for planarizing microscopic bumps and other surficial irregularities from wafer surfaces. CMP achieves such results from a combination of mechanical abrasion (using an abrasive in liquid suspension) and chemical action (using a mild surface-eroding chemical in the liquid suspension). More specifically, during CMP, the wafer surface is urged against a polishing pad, saturated with a polishing slurry, as the wafer and polishing pad undergo motion relative to each other. The polishing slurry is a suspension of polishing granules (silica, alumina, cerium oxide, or the like, depending on the material on the surface of the wafer) in an acidic or basic (depending on the material on the wafer surface) carrier liquid. With CMP, the entire surface of the wafer can be polished uniformly by making sure that the applied polishing pressure, amount of slurry used, and velocity of relative motions are uniform over the entire wafer surface.
Unfortunately, achieving consistent results with CMP is much more difficult than with other semiconductor processing steps such as layer-forming and etching. Therefore, there is a great need for improved methods for monitoring the thickness of the layer(s) on a wafer being polished by CMP, especially such methods that can provide quick, accurate, and efficient feedback to the CMP apparatus.
According to one conventional approach for monitoring polishing, changes in friction between the wafer and the polishing pad are monitored as corresponding changes in the torque being applied by a motor used to effect rotation of the wafer or polishing pad. For example, a change in torque is encountered when polishing has progressed to an underlying layer made of a material having a substantially different coefficient of friction than the layer being polished away. Unfortunately, monitoring polishing by monitoring torque is notoriously inaccurate and unreliable.
Optical methods for monitoring polishing offer prospects for high accuracy. According to one conventional method, a small wafer “blank” region (i.e., a location on a wafer where the surficial layer is essentially planar and desirably not patterned) is subjected to the same CMP process as the remainder of the wafer and used as a measurement sample. Measuring the thickness of the surficial layer as polishing progresses is performed by monitoring changes in the blank region.
Unfortunately, the “blank”-measurement method has several serious disadvantages. First, the method requires considerable time to execute and to provide feedback to the actual polishing process. Wafers are normally imprinted with as many devices as possible placed side by side. A non-imprinted portion, for use as a blank, of the wafer must be located among the devices on the wafer. The area of such a blank is normally very small and, on some wafers, has an unspecified location. Because the size of the blank region is normally very small, the range of measurements that can be performed at the location is also very small. Available apparatus for accurately measuring layer thickness within such a small area are simply not available. It is also very difficult to perform measurements in such a small area at sufficiently high speed because the required mechanism for picking up, recognizing, and processing the image of the blank region is very complex.
Also, positioning the wafer for measurement at the blank location poses many problems. Because the blank location is normally very small (and sometimes not even specified), accurate alignment mechanisms are required to ensure that the measurements are consistently performed at the blank location.
Another substantial contributor to the excessive amount of time required to perform the “blank” technique is the need to interrupt polishing, clean the wafer, and transport the wafer to a remote but stable location for measurement.
In another conventional optical method for monitoring polishing, the thickness of the layer being polished is monitored by optical interference. In such a technique, an optical path is provided through the polishing pad to the wafer surface being polished, and a laser light beam is directed through the polishing pad to the wafer surface during polishing. Alternatively, light (e.g., infrared light) is transmitted through the wafer holder and through the wafer from the rear surface of the wafer to the surface being polished. Temporal changes in the intensity of light reflected from the surface being polished are monitored as polishing progresses, and a polishing endpoint is believed to be reached when the intensity of the reflected laser light ceases to change with further polishing. Use of such a method for measuring the thickness of a layer at a “blank” location is normally effective in achieving a satisfactory accuracy. However, requisite accuracy is not obtained whenever the method is used to detect a polishing endpoint for a patterned layer (which must be performed when attempting to monitor polishing in real time as polishing progresses). This problem is even more pronounced when the wafer surface is patterned with logic circuits or a combination of logic and memory circuits.
Moreover, because the wafer undergoes motion during polishi
Ueda Takehiko
Ushio Yoshijiro
Berry Renee R.
Klarquist Sparkman Campbell & Leigh & Whinston, LLP
Nelms David
Nikon Corporation
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