Layer-stacked wiring and semiconductor device using the same

Details Layer-stacked wiring and semiconductor device using the same Layer-stacked wiring and semiconductor device using the same

2009-06-24

2010-12-14

Ho, Tu-Tu V (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

C257S059000, C257S066000, C257S057000, C257S754000, C257SE29292, C438S150000, C438S592000

Reexamination Certificate

active

07851807

ABSTRACT:
A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT (Thin Film Transistor) using the layer-stacked wiring, the microcrystalline silicon thin film is so configured that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of the microcrystalline silicon thin film amount to 15% or less of total number of crystal grains or that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of the microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains making up the microcrystalline silicon thin film.

REFERENCES:
patent: 4800177 (1989-01-01), Nakamae
patent: 6545407 (2003-04-01), Raina
patent: 2004/0195575 (2004-10-01), Komoda et al.
patent: 2006/0228897 (2006-10-01), Timans
patent: 3282582 (2002-03-01), None
patent: 2004-281506 (2004-10-01), None
patent: 2004-336073 (2004-11-01), None
patent: 3613221 (2004-11-01), None

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