Lattice based dynamic programming classification system

Details Lattice based dynamic programming classification system Lattice based dynamic programming classification system

1993-07-20

1995-12-05

Davis, George B.

395 22, 395 23, 395 24, 395 11, G06F 1518

Patent

active

054737311

ABSTRACT:
An integrated circuit lattice chip for computation of dynamic programming (DP) recursions uses identical nodal processor units arranged in regular lattice form. Interconnections between processor units on the chip are programmable using non-volatile EEPROM connections. The nodal processor units have computing element for generating a distance metric representative of the difference between the i.sup.th and j.sup.th elements of the unknown and prototype vectors that is combined with a maximum partial or minimum cumulative distance metric of preselected set of lower order nodal processors to produce an optimal (maximum or minimum) cumulative distance value for unknown and prototype vector elements with indices equal to or less than (i, j). A network is also provided for identifying the optimal path through the lattice for use in designing a DP classification system.

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