Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor
Reexamination Certificate
1999-11-16
2001-11-06
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Junction field effect transistor
C257S285000, C257S256000, C257S272000
Reexamination Certificate
active
06313489
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention is in the field of Semiconductor-On-Insulator (SOI) devices, and relates more particularly to lateral SOI devices suitable for high-voltage applications and a method of making such devices.
In fabricating high-voltage power devices, tradeoffs and compromises must typically be made in areas such as breakdown voltage, size, “on” resistance and manufacturing simplicity and reliability. Frequently, improving one parameter, such as breakdown voltage, will result in the degradation of another parameter, such as “on” resistance. Ideally, such devices would feature superior characteristics in all areas, with a minimum of operational and fabrication drawbacks.
One particularly advantageous form of lateral thin-film SOI device includes a semiconductor substrate, a buried insulating layer on the substrate, and a lateral transistor device in an SOI layer on the buried insulating layer, the device, such as a MOSFET, including a semiconductor surface layer on the buried insulating layer and having a source region of a first conductivity type formed in a body region of a second conductivity type opposite to that of the first, an insulated gate electrode over a channel region of the body region and insulated therefrom by a surface insulation region, a lightly-doped lateral region such as a lateral drift region of the first conductivity type, and a drain region of the first conductivity type laterally spaced apart from the channel region by the drift region.
A device of this type is shown in FIG. 1 common to related U.S. Pat. No. 5,246,870 (directed to a method) and U.S. Pat. No. 5,412,241 (directed to a device), commonly-assigned with the instant application and incorporated herein by reference. The device shown in FIG. 1 of the aforementioned patents is a lateral SOI MOSFET device having various features, such as a thinned SOI layer with a linear lateral doping region and an overlying field plate, to enhance operation. As is conventional, this device is an n-channel or NMOS transistor, with n-type source and drain regions, manufactured using a process conventionally referred to as NMOS technology. A more basic device is shown in U.S. Pat. No. 5,300,448, also commonly-assigned with the instant application and incorporated herein by reference.
More advanced techniques for enhancing high-voltage and high-current performance parameters of SOI power devices are shown in U.S. patent application Ser. No. 08/998,048, commonly-assigned with the instant application and incorporated herein by reference.
Thus, it will be apparent that numerous techniques and approaches have been used in order to enhance the performance of power semiconductor devices, in an ongoing effort to attain a more nearly optimum combination of such parameters as breakdown voltage, size, current-carrying capability and manufacturing ease. While all of the foregoing structures provide varying levels of improvement in device performance, no one device or structure fully optimizes all of the design requirements for high-voltage, high-current operation.
Accordingly, it would be desirable to have a transistor device structure capable of high performance in a high-voltage, high-current environment, in which operating parameters, and in particular breakdown voltage, and/or “on” resistance, are further optimized.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a transistor device structure capable of high performance in a high-voltage, high-current environment. It is a further object of the invention to provide such a transistor device structure in which operating parameters such as breakdown voltage and/or “on” resistance are enhanced.
In accordance with the invention, these objects are achieved in a lateral thin-film SOI device structure of the type described above in which a lightly-doped lateral region (typically the drift region) is provided with a retrograde doping profile such that the doping profile at a portion of the lateral region adjacent the buried insulating layer is greater than the doping at a portion of the lateral region adjacent the surface insulation region.
In a preferred embodiment of the invention, an arsenic doping is used to obtain the retrograde doping profile, and the doping at the portion of the lateral drift region adjacent the buried insulating layer is about 50% greater than the doping at the portion of the lateral drift region adjacent the surface insulation region.
In a further preferred embodiment of the invention, devices in accordance with the invention are made by a method in which the semiconductor substrate is doped with a desired dopant, the semiconductor substrate is oxidized to form the buried insulating layer containing the dopant, an SOI layer is formed on the buried insulating layer containing the dopant, and the dopant is thermally diffused from the buried insulating layer into the SOI layer to form the retrograde doping profile.
Lateral thin-film SOI devices in accordance with the present invention offer a significant improvement in that a combination of favorable performance characteristics making the devices suitable for operation in a high-voltage, high-current environment, and in particular high breakdown voltage and/or reduced “on” resistance, can be achieved.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
REFERENCES:
patent: 5246870 (1993-09-01), Merchant
patent: 5300448 (1994-04-01), Merchant et al.
patent: 5378920 (1995-01-01), Nakagawa et al.
patent: 5401982 (1995-03-01), King et al.
patent: 5412241 (1995-05-01), Merchant
patent: 5420457 (1995-05-01), Shibib
patent: 5426325 (1995-06-01), Chang et al.
patent: 5744851 (1998-04-01), Beasom
patent: 5767547 (1998-06-01), Merchant et al.
patent: 5849627 (1998-12-01), Linn et al.
patent: 5973341 (1999-10-01), Letavic et al.
patent: 6140170 (2000-10-01), Shibib
patent: 08064686 (1996-03-01), None
patent: 08181321 (1996-07-01), None
patent: 08181321A (1996-07-01), None
“SOI Device Structures Implementing 650 V High Voltage Output Devices on VLSIs”, by N. Yasuhara et al., Proceedings of the International Electron Devices Meeting.
Egloff Richard
Letavic Theodore
Simpson Mark
Warwick Andrew Mark
Biren Steven R.
Meier Stephen D.
Philips Electronics North America Corporation
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