Active solid-state devices (e.g. – transistors – solid-state diode – Punchthrough structure device
Reexamination Certificate
1997-11-12
2001-07-17
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Punchthrough structure device
C257S494000, C257S495000, C257S498000
Reexamination Certificate
active
06262466
ABSTRACT:
BACKGROUND INFORMATION
The present invention starts out from a lateral semiconductor structure having a punch-through diode for forming a temperature-compensated voltage limitation. It is already known to use punch-through diodes for voltage limitation in silicon semiconductor structures. Punch-through diodes are p
+
np
+
or rather n
+
pn
+
silicon structures in which the width and doping of the middle region are chosen so that when a voltage is applied to the two outer layers, no avalanche effect or rather zener effect occurs. If the voltage is increased, the space charge region of the blocking pn junction expands until it contacts the opposite junction. This pn junction operated in the conducting state injects charge carriers into the field of the space charge region, i.e., the current increases significantly starting at this voltage. The current/voltage characteristic curve of a punch-through diode is, at least for certain current densities, practically independent of temperature. In the space charge region, there exists for sufficiently high current densities a linear relationship between the current and the voltage, which is known as the space charge resistance. This space charge resistance is proportional as an approximation to the square of the expansion of the middle region. Since the punch-through voltage increases more or less with the square of the width of the middle region, the space charge resistance increases linearly for increasing voltage. Here, the problem arises that for high limitation voltages, the space charge resistance increases undesirably significantly. The known punch-through diodes are thus suited only to relatively small current densities.
SUMMARY OF THE INVENTION
In contrast, the lateral semiconductor structure according to the present invention has the advantage that the space charge resistance is decreased so that higher limitation voltages can also be attained with punch-through diodes. This is achieved advantageously in that one of the semiconductor regions of the same kind is designed as a floating region.
Another embodiment of the present invention utilizes a specified separation between the base trough and the further p-doped region which determines as a first approximation the resistance of the space charge region. Since the space charge region in the further p-doped region is not so sharply formed as in the weakly n-doped region, a smaller space charge resistance overall is obtained with the arrangement according to the present invention. Accordingly, a higher breakdown voltage can be achieved advantageously for the same blocking-state current.
Due to the partial overlapping of the further p-doped region with the highly n-doped region, a smaller separation from the edge region of the structure is obtained advantageously so that the semiconductor structure can be designed smaller overall.
Yet another embodiment of the present invention to obtain a further reduction of the space charge resistance is achieved in that a specified separation is provided between the further p-doped region and the highly n-doped region. Through the choice of a suitable separation between the further p-doped region and the highly n-doped region, the avalanche breakdown voltage can be influenced.
If a third p-doped region is inserted between the base trough and the further p-doped region, the resistance of the breakdown characteristic curve is reduced even further. It is also advantageous that no avalanche breakdown is required so that the reverse voltage is independent of temperature for certain current densities.
Since the semiconductor structure can be designed with npn as well as with pnp structures, a universal application is possible, in particular for base collector (BC) clamping of power transistors or switching transistors. Such structures are connected advantageously on a chip with integrated circuits.
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Kenyon & Kenyon
Loke Steven
Robert & Bosch GmbH
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