Lateral semiconductor device and vertical semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Lateral bipolar transistor structure

Reexamination Certificate

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C257S401000, C257S578000

Reexamination Certificate

active

06650001

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 USC 119 to Japanese Patent Application No. 2001-16624, filed on Jan. 25, 2001 and Japanese Patent No. 2001-381449, filed on Dec. 14, 2001, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
The present invention relates to a lateral semiconductor device, particularly, a lateral insulated gate bipolar transistor (to be simply referred to as an IGBT hereinafter), and to a vertical semiconductor device, particularly, a vertical IGBT.
An IGBT as a insulated gate type high-voltage semiconductor device is a voltage-controlled semiconductor device. Since this facilitates the formation of a gate circuit, an IGBT is widely used in the field of power electronics such as inverters and switching power supplies. In particular, an IGBT is a power device having both high-speed switching characteristics of a MOSFET and high-output characteristics of a bipolar transistor. Also, a lateral IGBT which is advantageous in high integration is often used as an output device of a power IC. A power IC including a plurality of output devices is in many times fabricated using an SOI (Semiconductor On Insulator) substrate which is advantageous in dielectric isolation.
A lateral IGBT of this type related to the present invention will be explained below with reference to
FIGS. 24 and 25
.
FIG. 24
is a plan view of the IGBT.
FIG. 25
is a sectional view taken along a line A-A′ in FIG.
24
.
An SOI substrate
1101
has a support substrate
1102
, a buried oxide film
1103
, and an n

-type base layer
1104
. An n-type buffer layer
1105
is formed in the surface of the n

-type layer
1104
by selective diffusion. This n-type buffer layer
1105
has a stripe shape whose two end portions protrude outward into the shape of an arc. A p-type drain layer
1106
is formed in the surface of the n-type buffer layer
1105
by selective diffusion. This p-type drain layer
1106
has the same shape as the n-type buffer layer
1105
.
In the surface of the n

-type base layer
1104
, a p-type base layer
1107
is formed by selective diffusion so as to surround the n-type buffer layer
1105
. The inner circumferential surface of this p-type base layer
1107
has the same shape as the n-type buffer layer
1105
. Striped n
+
-type source layer
1108
are formed in portions of the p-type base layer
1107
by selective diffusion on the two sides of the p-type drain layer
1106
. These n
+
-type source layers
1108
have substantially the same length as the straight portion of the p-type drain layer
1106
.
On the p-type base layer
1107
sandwiched between the n

-type base layer
1104
and the n
+
-type source layers
1108
, a gate electrode
1110
is formed via a gate insulating film
1109
. This gate electrode
1110
is formed into an annular structure so as to surround the n-type buffer layer
1105
. The inner circumferential surface of the gate electrode
1110
has the same shape as the outer circumferential surface of the n-type buffer layer
1105
. In addition, a gate line
1113
for extracting the gate electrode to the outside is formed in a portion of the gate electrode.
An insulating film
1111
is formed on the exposed surfaces of the gate electrode
1110
and the n

-type base layer
1104
. A drain line
1112
and a source line
1114
are formed on this insulating film
1111
. Contact holes
1115
are formed in predetermined positions of the insulating film
1111
. Through these contact holes
1115
, the drain line
1112
is in ohmic contact with the p-type drain layer
1106
, and the source line
1114
is in ohmic contact with the p-type base layer
1107
and the n
+
-type source layer
1108
.
To obtain a high breakdown voltage in this lateral IGBT, a curvature R of the arc at the two end portions of the n-type buffer layer
1105
must be increased to some extent. To this end, a width Lb of the n-type buffer layer
1105
must be increased. If this width Lb of the n-type buffer layer
1105
is increased, the width of the p-type drain layer
1106
also increases, and this inevitably increases the area of the p-type drain layer
1106
.
However, it is found by the experiments conducted by the present inventors that when the area of the p-type drain layer
1106
is increased by increasing the width Lb of the n-type buffer layer
1105
, the ON voltage of the IGBT rises.
FIG. 26
is a graph showing the relationship between the area of the p-type drain layer and the ON voltage of the IGBT. As shown in
FIG. 26
, this IGBT has the problem that when the width Lb of the n-type buffer layer
1105
is increased in order to obtain a high breakdown voltage, the area of the p-type drain layer
1106
increases, and this raises the ON voltage.
A vertical IGBT relevant to the present invention will be described next.
FIG. 27
is a longitudinal sectional view showing this vertical IGBT.
This IGBT includes a drain electrode
1201
, a p-type drain layer
1202
, an n-type buffer layer
1203
, an n

-type base layer
1204
, a p-type base layer
1205
, an n
+
-type source layer
1206
, a gate insulating film
1207
, a gate electrode
1208
, and a source electrode
1209
.
In this structure, when a voltage which is positive with respect to the source electrode
1209
is applied to the gate electrode
1208
while a voltage which is positive with respect to the source electrode
1209
is applied to the drain electrode
1201
, the n
+
-type source layer
1206
is electrically connected to the n

-type base layer
1204
via a channel formed on the surface of the p-type base layer
1205
below the gate electrode
1208
, so electrons are injected into the n

-type base layer
1204
. Also, holes in an amount corresponding to the injected electrons are injected from the p-type drain layer
1202
into the n

-type base layer
1204
.
This lowers the resistance of the high-resistance n

-type base layer
1204
by conductivity modulation. Accordingly, the ON voltage can be made lower than that of a MOSFET having the same forward-blocking characteristics.
To turn off this IGBT, the application of the positive voltage to the gate electrode
1208
need only be stopped. Consequently, the injection of electrons into the n

-type base layer
1204
stops, and the injection of holes stops accordingly. However, electrons and holes remaining in the n

-type base layer
1204
keep flowing for a while as a recombination current which depends upon the lifetime of the n

-type base layer
1204
, and a drift current resulting from the spread of a depletion layer caused by the voltage rise.
To reduce the loss upon turning-off of the IGBT while the ON voltage is kept low, therefore, as shown in
FIG. 28
, it is necessary to increase the carrier amount in the source electrode
1209
and reduce the carrier amount in the drain electrode
1201
. This is so because the depletion layer extends from the source and carriers in the drain remain to the last.
As a method of reducing the carrier amount in the drain, a method using the lightly doped p-type drain layer
1202
is proposed in the following reference.
J. Fugger et al., “Optimizing the vertical IGBT structure—The NPT concept as the most economic and electrically ideal solution for a 1200V IGBT”, Proceedings of the 8th ISPSD, pp. 169-172, 1996.
In this method, it is necessary to form the n-type buffer layer
1203
at a minimum necessary concentration in order to hold the forward-blocking voltage, and to form the p-type drain layer
1202
at a low concentration in order to suppress the injection of holes.
The p-type drain layer
1202
is formed by ion implantation of boron and diffusion of the boron by high-temperature annealing. However, surface recession caused by the diffusion lowers the surface concentration of the boron, so no ohmic contact to the drain electrode
1201
can be formed, and injection of holes hardly occurs. Also, since the implantation do

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