Active solid-state devices (e.g. – transistors – solid-state diode – With specified impurity concentration gradient – With high resistivity
Reexamination Certificate
2000-12-12
2002-07-30
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With specified impurity concentration gradient
With high resistivity
C257S075000, C257S067000
Reexamination Certificate
active
06426547
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to PIN diodes and particularly a diode structure wherein the various conductive regions are laterally disposed.
BACKGROUND
Electronic switches are key for a large variety of applications, in particular, the very high volume consumer wireless 1-2 GHz market where they serve to switch the antenna in a mobile phone between receive and transmit circuits. A good switch must possess several important properties. First, the resistance should be low when the switch is on. Second, the isolation should be good when the switch is off. Finally, the switch should be able to handle a signal of sufficient strength without distorting it (i.e. without the signal itself causing the switch to turn further on or off compared to its initial state).
One type of switch has been very successful at high frequencies is the PIN diode, which consists of an intrinsic or “I” region sandwiched between P and N regions. When this diode is reverse biased (P region at a negative voltage compared with the N region), the switch is off. When the diode is forward biased, the switch turns on. In addition, a great deal of charge gets stored in the “I” region of the device. This charge serves two purposes—it helps reduce the resistance of the switch, and, since the charge must be removed to turn the switch off, it slows down the speed at which the switch can go from on to off. This is important because it means that high-frequency signals passing through the switch won't influence the on/off state of the switch itself (i.e. a large signal excursion won't turn the switch off). Thus, an important factor for good PIN diode performance is the volume of stored charge. The volume of stored charge, in turn, is related to two numbers—the volume of the I region, and the lifetime of carriers in the I region.
It is standard in the art to make individual, discrete PIN diodes comprising large I regions. However, customers increasingly require integrated solutions. For reasons of cost, reliability, and compactness, customers want to be able to put switches directly on the chips that implement their RF transmitters and receivers, to make complete or partial systems-on-a-chip.
The current state of RF technologies, for example silicon-germanium BiCMOS, tends to build all the transistors and other front-end-of-the-line devices in a thin epitaxial layer grown on top of a substrate. The current art limits the dimensions of the I region, and therefore the charge capacity of prior art, vertically-disposed PIN diodes, by the thickness of the epitaxial layer. Typically, the process commences with a substrate into which is implanted a heavily-doped N
+
subcollector layer. A thin, typically less than 1 micrometer, epitaxial layer is grown over the N
+
layer. The N+ layer diffuses upward leaving at most a 0.5 micrometer layer to comprise the I-region. There simply isn't enough thickness of material to make a large I region in a PIN diode by growing the I-layer in the vertical direction.
A need exists for a PIN diode having a sufficiently large I-region that is capable of being integrated into modern RF processes.
A need exists for such a PIN diode capable of being fabricated using typical processing steps current in the art of making such RF devices. Such a PIN diode would then come substantially for free with current process steps.
Other objects and advantages will become apparent from the following disclosure.
SUMMARY OF INVENTION
The present invention provides an improved and novel lateral PIN diode structure that laterally extends the intrinsic region thereby extending the charge storage area. The present invention provides for reduced parasitic capacitance by placing the diode on an oxide layer.
The present invention provides a lateral PIN diode comprising large-grained polysilicon and having an extended intrinsic region formed over thick oxide isolation.
Referring to
FIG. 2
, the present invention provides an extended charge storage, lateral PIN diode comprising a first semiconductor layer (
1
) of a first conductivity type; field isolation means (
2
) formed on a major surface of said first semiconductor layer; a second semiconductor layer (
4
) formed above and on a major surface of said field isolation means, wherein said second semiconductor layer comprises N-type, intrinsic, and P-type regions, and wherein said intrinsic region lies between and abuts said N-type and said P-type regions; an oxide film (
7
) formed on a major surface of said second semiconductor layer; and a masking module which module may optionally be an emitter module, formed on a major surface of said oxide film wherein said masking module is aligned above said intrinsic region and wherein said masking module masks the edges of the N-type and P-type regions.
The present invention provides a extended charge storage, lateral PIN diode optionally comprising: an opening formed through said field isolation means communicating with said first semiconductor layer; wherein a portion of said second semiconductor layer fills said optional opening and abuts said first semiconductor layer.
The present invention provides that the PIN device comprises, in a first embodiment, large-grain silicon, and in a preferred embodiment, comprises single crystal silicon.
The present invention provides a means of making a PIN diode with an enlarged I-region such that can be integrated into a modem RF process. The present invention provides that the current flows laterally instead of vertically and scales the I-region by enlarging the lateral dimension between the P and N regions.
The present invention uses process steps common to typical RF device fabrication so that much of the PIN diode comes for free with the existing process. The present invention uses several such steps for free. First, the body of the PIN diode is formed from the layer emplaced for the base of the bipolar transistor and/or the gates of the FETs. Second, the invention provides that the emitter module is used to mask off the I-region during subsequent implantation of the P and N contacts of the diode.
The present invention employs polysilicon as the initial material from which the body of PIN is made. Polysilicon doesn't have a great carrier lifetime because carriers can recombine at grain boundaries. This serves to decrease the stored charge, counteracting our attempt to make a large I-layer.
The first embodiment of the invention provides a PIN that can be integrated into an RF chip and which comes for free with the conventional processing steps. This embodiment provides an implant to amorphize the polysilicon and then an anneal step to regrow it as large grain polysilicon to reduce the grain boundaries and improve the carrier lifetime.
In a second embodiment of the invention, the polysilicon comprising the PIN diode layer is caused to pass through an opening in the underlying dielectric layer and to contact the single crystal substrate. The polycrystalline silicon is amorphized and annealed. The surface of the single crystal silicon acts as a seed causing the PIN diode layer to recrystallize as single crystal silicon in a process known as solid phase epitaxy. Thus the I-layer of the PIN diode will be caused to have high carrier lifetimes.
The invention further provides reduced parasitic capacitances by virtue of building the PIN diode in its own layer atop a layer of isolation oxide (or other dielectric) instead of building the PIN diode into the bulk silicon.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illus
Greenberg David R.
Jadus Dale K.
Subbanna Seshadri
Walter Keith M.
Connolly Bove Lodge & Hutz
Information Business Machines Corporation
Townsend, Esq. Tiffany L.
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