Lateral junction field effect transistor and method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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C257S272000, C257S285000, C257SE27069

Reexamination Certificate

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07420232

ABSTRACT:
A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

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N. Kaminski et al., “Punch-through behaviour of wide bandgap materials (with example in 6H-SiC) and its benefit to JFETS”, Materials Science Forum (264-268):1073-1076 (1998).

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