Lateral high-Q inductor for semiconductor devices

Details Lateral high-Q inductor for semiconductor devices Lateral high-Q inductor for semiconductor devices

1999-10-12

2001-09-18

Mai, Anh (Department: 2832)

Inductor devices

Coil or coil turn supports or spacers

Printed circuit-type coil

C336S223000, C336S232000

Reexamination Certificate

active

06292086

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
Not Applicable
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT
Not Applicable
FIELD OF THE INVENTION
This invention relates to the manufacturing of semiconductor devices. More specifically, the invention relates to a lateral inductor on a semiconductor device.
BACKGROUND OF THE INVENTION
High-Q inductors are a common feature found on most communications semiconductor devices. The most common method of forming an inductor in a semiconductor device involves depositing thick layers, 3 &mgr;m or greater, of metal on the top layer of circuitry. This top layer is formed in a spiral pattern in conjunction with a special substrate to create a high-Q inductor. This method has the disadvantage in that to create an inductor of
10
, an area of typically more than 300 &mgr;m×300 &mgr;m is required. This area subsequently cannot be used for other circuitry due to electromagnetic interference. Additionally, current processing techniques to form these high-Q inductors that use photoresist and copper require two or more mask levels and two or more exposure steps. This processing results in inductors with air gaps that are not compatible with current processing technology.
Previous attempts have been made at creating lateral high-Q inductors on either non-conducting or highly resistive substrates. However, current chip designs prefer highly conductive substrates for latch-up protection. Current versions of high-Q inductors on silicon substrates have been demonstrated with planar spiral inductors in AlCu, but this technology is not compatible with upper level copper metalization.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a high-Q lateral inductor that provide reduced area requirements in a semiconductor device.
It is yet another object of the invention to provide a high-Q lateral inductor that can be used with copper damascene processes.
It is another object of the invention to provide a high-Q lateral inductor that only requires a single mask step.
It is a further object of the invention to provide a high-Q lateral inductor that can be easily modeled using readily available analytical tools.
It is still another object of the invention is to provide a high-Q lateral inductor that is CMOS compatible.
Yet another object of the invention is to provide a high-Q lateral inductor that is compatible with silicon substrates.
These and other objects of the invention are achieved by the subject device comprising a plurality of loops connected in series and formed along a lateral axis of a semiconductor device. Each loop comprises a bottom leg, a top leg, and a pair of side legs. The bottom legs are parallel and extend along a first plane. The top legs are also parallel and extend along a second plane. The second plane is parallel to and separate from the first plane. The first and second planes are parallel to said lateral axis, and the side legs are perpendicular to the first and second planes.
The top and side legs can be formed from copper. If the top and side legs are formed from copper, a tantalum nitride or other copper barrier layer between the top legs and a substrate layer adjacent the top legs and between the side legs and the bottom legs and the substrate layer is preferably provided.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are described below. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety. In case of conflict, the present specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and not intended to be limiting.


REFERENCES:
patent: 4926292 (1990-05-01), Maple
patent: 5425167 (1995-06-01), Shiga et al.
patent: 5576680 (1996-11-01), Ling
patent: 56 120155 (1981-09-01), None
Ahn et al, A Fully Integrated Planar Toroidal Inductor with a Micromachined Nickel-Iron Magnetic Bar, IEEE Transactions on Components, packaging and manufaturing technolody-Part A, vol. 17, No. 3, Sep. 1994.

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