Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of...
Reexamination Certificate
2002-10-11
2004-06-29
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
C257S197000
Reexamination Certificate
active
06756278
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a lateral heterojunction bipolar transistor and to a method of fabricating the same. More particularly, it relates to a lateral heterojunction bipolar transistor having a heterostructure such as Si/Si
1-x
Ge
x
or Si/Si
1-x-y
Ge
x
C
y
formed on an insulating substrate such as SOI (Silicon on Insulator).
There has conventionally been proposed technology for providing a transistor with excellent characteristics by forming a CMOS device and a bipolar transistor on a SOI (Silicon on Insulator) substrate composed of a silicon layer stacked on an insulating layer to lower the operating voltage of the transistor, provide a complete isolation between devices, and reduce a parasitic capacitance. In transmitting/receiving portions of a communication device handling an RF signal, in particular, a crosstalk between an analog circuit and a digital circuit presents a problem. However, the use of the SOI substrate holds promise of removing the crosstalk more drastically than the conventional technology.
On the other hand, a heterojunction bipolar transistor using a heterostructure such as Si/SiGe has been used commercially in recent years as a device operable in a region of RF frequencies, which has been considered difficult to fabricate by using the technology using a silicon process. Compared with a Si homojunction bipolar transistor, the heterojunction bipolar transistor has an excellent characteristic such that the resistance of a base can be reduced by adjusting the impurity concentration in the base to be higher than in the Si homojunction bipolar transistor since reverse injection of carriers from the base to an emitter is suppressed by using the heterostructure in which the band gap of the base is smaller than the band gap of the emitter.
In response to the system-on-chip demand made in recent years, BiCMOS technology has been requested to form a CMOS device and a bipolar transistor on a single chip. To form the bipolar transistor on a SOI substrate, however, it is necessary to increase the thickness of a silicon layer to a certain degree in a conventional vertical bipolar transistor structure, while it is necessary to reduce the thickness of the silicon layer in the CMOS device for high-speed operation and the suppression of a leakage current. However, the provision of a silicon layer having different thicknesses in a CMOS device region and a bipolar transistor region increases the complexity of the fabrication process.
To use a silicon layer having the same thickness in the bipolar transistor region as in the CMOS device region, there has been proposed the formation of a lateral heterojunction bipolar transistor on a SOI substrate. By using a lateral heterojunction bipolar transistor structure, the silicon layer having the same thickness in the both regions can be used and the process steps are greatly reduced in number. It has also been reported that a parasitic resistance is smaller in the lateral heterojunction bipolar transistor structure than in the vertical bipolar transistor formed by using a SOI substrate, which is advantageous in terms of high-speed operation.
FIGS.
10
(
a
) and
10
(
b
) are a plan view and a cross-sectional view of a lateral heterojunction bipolar transistor provided on a SOI disclosed in a document about an example of a prototype of such a lateral heterojunction bipolar transistor (A 31 GHz f
max
Lateral BJT on SOI Using Self-Aligned External Base Formation Technology: T. Shino et. al. 1998 IEEE). As shown in the drawings, the lateral heterojunction bipolar transistor is formed on a SOI substrate including a BOX layer
1001
composed of a silicon oxide film and a silicon layer
1009
. By using the SOI substrate, a parasitic capacitance in the operating region of the transistor can be reduced. The thickness of the silicon layer
1009
is 0.1 &mgr;m. The silicon layer
1009
comprises: a strip-like p-type internal base layer
1004
doped with boron (B); two external base layers
1006
connected to the shorter side portions on both ends of the internal base layer
1004
and doped with boron (B) at a concentration higher than that in the internal base layer
1004
; and an n-type emitter
1005
and an n-type collector
1002
disposed with the longer side portions of the internal base layer
1004
interposed therebetween. The emitter
1005
has been doped with arsenic (As) at a high concentration and the collector
1002
has been doped with arsenic at a non-uniform concentration. In short, the collector
1002
has a retrograde structure in which the concentration of arsenic is lower for an increased breakdown voltage in the portions thereof closer to the internal base layer
1004
and the external base layers
1006
, which increases gradually with distance from the internal base layer
1004
and the external base layers
1006
. The respective electrode formation portions of the external base layers
1006
, the emitter
1005
, and the collector
1002
are located on the respective outward tips of the regions such that the longest possible distances are provided therebetween and that parasitic capacitances among base electrodes, an emitter electrode, and a collector electrode are reduced. The foregoing document reports that such a lateral heterojunction bipolar transistor has provided a maximum oscillation frequency fmax of 31 GHz.
FIGS.
11
(
a
) to
11
(
e
) are perspective views illustrating a method of fabricating the bipolar transistor disclosed in the document.
First, in the step shown in FIG.
11
(
a
), an oxide film and a SiN film (not shown) are formed on the n-type silicon layer
1009
into which phosphorus (P) has been introduced. Then, an array-like resist mask
1108
is formed on the SiN to cover an NPN active region. Subsequently, boron (B) is ion implanted at a dose of 4×10
15
atoms·cm
−2
into the silicon layer
1009
except for the NPN active region
1107
from above the resist mask
1108
, whereby a P
+
diffused region is formed. Next, in the step shown in FIG.
11
(
b
), the SiN film is patterned by using the resist mask
1108
as a mask and side etched to form a SiN mask
1110
, which is inwardly offset by about 0.2 &mgr;m from the ends of the resist mask
1108
. Thereafter, the resist mask
1108
is removed. Then, in the step shown in FIG.
11
(
c
), a TEOS mask
1111
is formed in crossing relation to the SiN mask
1110
. Subsequently, boron (B) is ion implanted at a dose of 1×10
14
atoms·cm
−2
and an acceleration energy of 25 keV into the silicon layer
1009
except for the region covered with the SiN mask
1110
and the TEOS mask
1111
. Next, in the step shown in FIG.
11
(
d
), the SiN mask
1110
and the TEOS mask
1111
are removed. At this time, the width of the internal base layer
1004
is determined by the diffusion distance traveled by implanted boron, which is measured from the end portion of the TEOS mask
1111
. Finally, in the step shown in FIG.
11
(
e
), portions serving as the emitter and the collector are mesa etched and arsenic (As) is ion implanted into the respective portions at a dose of 1×10
15
atoms·cm
−2
and an acceleration voltage of 120 keV and at a dose of 1×10
15
atoms·cm
−2
and an acceleration voltage of 65 keV. Since the silicon layer
1009
is amorphized by the ion implantations, it is recrystallized by RTA performed at 1050° C. for 20 sec and by electric furnace annealing performed at 850° C. for 60 sec.
By the foregoing process, a lateral bipolar transistor with a small parasitic capacitance which is high in fmax and operable at a high speed can be formed.
However, since the width of the internal base
1104
is determined by the diffusion distance of boron in accordance with the prior art technology disclosed in the foregoing document, it is difficult to constantly obtain a desired impurity distribution. Since the range in which the emitter
1105
and the collector
1102
are formed is determined by the diffusion distance of the n-type impurity, it is also difficult to form a pn ju
Kubo Minoru
Yuki Koichiro
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Nelms David
Vu David
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