Lateral DMOS design for ESD protection

Details Lateral DMOS design for ESD protection Lateral DMOS design for ESD protection

1998-06-17

2000-05-16

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

327330, H04H 904

Patent

active

060642491

ABSTRACT:
A LDMOS having improved ESD reliability and a method for designing such a LDMOS. A higher gate clamp voltage and/or minimized drain clamp voltage is used to maximize the ESD performance of the LDMOS. Given a set of design parameters, one or more of the gate clamp voltage, drain clamp voltage, or size of the LDMOS are optimized to meet the design parameters while achieving the optimum ESD performance.

REFERENCES:
patent: 5654863 (1997-08-01), Davies
patent: 5767550 (1998-06-01), Calafut et al.
patent: 5917220 (1999-06-01), Waggoner
1997 IEEE, IEDM 97-375, "Lateral DMOS Design for ESD Robustness," pp. 14.7.1-14.7.4 (Charvaka Duvvury, Fred Carvajal, Clif Jones and David Briggs).

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