Lateral bipolar transistor and method of making same

Details Lateral bipolar transistor and method of making same Lateral bipolar transistor and method of making same

1999-08-26

2003-08-26

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

With specified electrode means

C257S557000, C257S558000, C257S561000, C257S587000, C257S591000, C257S592000, C438S339000, C438S372000, C438S373000

Reexamination Certificate

active

06611044

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a lateral bipolar transistor for an integrated circuit and a method of manufacturing the lateral bipolar transistor, and, more particularly, to a bipolar and complementary MOS transistor (BiCMOS) circuit using the lateral bipolar transistor and its method of manufacture.
2. Description of the Related Art
BiCMOS circuits including high speed analog circuitry are in high demand for computer and communication applications. A conventional BiCMOS circuit has both bipolar transistors and MOS transistors and in a single circuit on a common substrate. MOS transistors are typically used in digital circuits while bipolar transistors are typically used in analog circuits, and a BiCMOS circuit combines and integrates these transistors in a common monolithic semiconductor structure. Accordingly, in fabricating BiCMOS circuits, the formation of the MOS transistors and bipolar transistors must be compatible to be integrated into a common process scheme. Moreover, to control production cost, time and complexity, there remains a constant need in the BiCMOS process field for new design approaches that limit and reduce the overall number of process steps.
Lateral bipolar type transistors are used in BiCMOS devices as they provide good linearity and they generally are amenable to high volume production. The lateral bipolar transistors generally involve three distinct semiconductor regions of alternating conductivities, e.g., PNP or NPN, which extend along a common surface region of a substrate so as to form a lateral PNP (LPNP) or lateral NPN (LNPN), respectively. A need exists for a process sequence that would accomodate formation of a lateral bipolar transistor (e.g., LPNPs) for a BiCMOS circuit in the same area otherwise defined for a vertical bipolar device (viz., a vertical NPN device) without requiring additional process steps compared to those required to form vertical bipolar devices in the BiCMOS process. It also would be desirable to reduce the lateral spacing between emitters and collectors in LPNPs of BiCMOS devices. Narrower spacing between emitters and collectors in LPNPs is conducive to increasing gain and frequency response in the devices.
Additionally, for analog circuits in general using bipolar transistors, the magnitude of the current gain, maximum operating frequency, and Early voltage properties generally provide an indication of the high speed capabilities of the circuitry. Moreover, larger values of the product of the beta (&bgr;) value (i.e., the current gain) of the transistor times the Early voltage also provides an indication of the high performance capabilities of the circuit. As known, a transistor's beta (&bgr;) value is the ratio of its output current (I
C
) to its input current (I
B
) determined while the transistor's collector-to-emitter voltage (V
CE
) is held constant. The current gain of a transistor circuit corresponds identically to the transistor's beta (&bgr;) value for a common-emitter transistor circuit.
The Early effect phenomenon is also well known and it is based upon experimental observations that when the output characteristics curves, i.e., the plots of measured data of collector current versus collector voltage for different base current, of a bipolar transistor are extrapolated back to the point of zero collector current, that the curves all intersect at a common negative voltage. This voltage is the Early voltage, and it is typically represented as V
A
. High Early voltage is desired in analog circuits to prevent drastic swings from occuring in the collector current.
However, an impediment in the past to improving the high speed performance of an analog circuit with lateral bipolar transistors has been a tradeoff relationship that exists between the Early voltage, on one hand, and the current gain or the operational frequency on the other. Namely, improvements (increases) provided in either current gain or Early voltage in prior bipolar transistor designs have tended to be accompanied by an offsetting reduction in the other property such that the net overall performance of the circuit was not significantly improved. For example, the product of current gain (or beta) times the Early voltage, as a measure of performance capability, would remain essentially the same in value because if one property was increased the other property would seesaw down a cancelling amount. Therefore, a need also exists for lateral bipolar transistor architecture permitting enhancements to be made to either the Early voltage or the current gain (or operational frequency) without the improvements being effectively cancelled out due to an offsetting reduction occuring in the other transistor property. In that way, a meaningful net improvement in circuit performance might be provided at the design level.
In any event, the prior art fails to satisfactorily address and meet one or more of the above-mentioned needs and problems associated with conventional semiconductor devices using lateral bipolar transistors in general and conventional BiCMOS technology in particular.
For instance, U.S. Pat. No. 5,187,109 describes a process for making BiCMOS integrated circuits which include a bipolar transistor and MOS transistors. The emitter and collector are located in the same active region with a remote base contact made to a buried N region. The emitter is formed by diffusion from a layer of P+ polycrystalline silicon, and the P+ polycrystalline layer also serves as the gates of the MOS transistors. The base region is located directly under an insulator which is covered by the P+ polycrystalline layer used to form the emitter. A P+ S/D of the PMOS is the collector, and it is self-aligned to the base. An emitter field plate is used that is self-aligned to the collector to minimize E-C capacitance. The device is isolated with a buried N connection to cathode. A polycrystalline layer is used to contact deep buried N regions, and a CMOS spacer is used to prevent a short to the anode. However, U.S. Pat. No. 5,187,109 fails to teach a lateral bipolar transistor architecture in which the current gain or Early voltage can be enhanced without sacrificing the other property in a proportional manner.
Sun, et al.,
IEEE Transactrions on Electron Devices
, vol. 39, no. Dec. 12, 1992, pp. 2733-2739, and commonly assigned U.S. Pat. No. 5,824,560, describe BiCMOS process technology providing a gated lateral PNP with metal silicide contacts arranged on the surface of polysilicon electrodes and on adjacent P+ surface regions provided in the substrate, where conventional lateral insulation portions or oxide spacers are formed on the sides of the polysilicon electrodes before subsequent metal silicide processing is performed, and the oxide spacers laterally intervene and laterally space the polysilicon electrodes from the P+ surface regions, and hence increases the spacing between adjacent polysilicon electrodes. Therefore, the gain and frequency response in the devices described in the Sun et al. publication and the U.S. Pat. No. 5,824,560 patent can be expected to be non-optimal. Additionally, as with the U.S. Pat. No. 5,197,109 patent, the Sun et al. publication and the U.S. Pat. No. 5,824,560 patent also fail to teach a lateral bipolar transistor architecture in which the current gain or Early voltage can be favorably improved without sacrificing the other property in a proportional manner.
Consequently, a need has existed in the art for a lateral bipolar transistor architecture that would support and enable high performance, high speed BiCMOS circuits technology, and a methodology for assimilating the formation of such bipolar transistor architecture into a BiCMOS process without necessitating additional process steps. The present invention fulfills the above and other needs.
SUMMARY OF THE INVENTION
According to the present invention, a lateral bipolar transistor is provided that maintains a high current gain and high frequency capability without sacrificing high E

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