Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Forming lateral transistor structure
Reexamination Certificate
2000-10-13
2003-01-07
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Forming lateral transistor structure
C438S341000, C438S350000
Reexamination Certificate
active
06503808
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for producing the same. In particular, the present invention relates to a lateral home-junction or hetero-junction bipolar transistor incorporating an SOI. (silicon on insulator) substrate, and a method for producing the same.
2. Description of the Related Art
FIG. 4
is a schematic cross-sectional view illustrating the structure of an npn-type vertical hetero-bipolar transistor (HBT) composed of SiGe/Si and produced by a conventional technique.
In accordance with this conventional vertical HBT, an n
+
type Si collector contact layer
302
, an n
−
type Si collector layer
303
, a p type SiGe true base region (layer)
304
, a p
+
type SiGe external base region (layer)
305
, an n type Si emitter layer
306
, and an n
+
type Si emitter contact layer
307
are layered in this order on a silicon substrate
301
. A collector electrode
308
is formed on an exposed surface of the n
+
type Si collector contact layer
302
which is formed by local etching. A base electrode
309
is formed on an exposed surface of the p
+
type SiGe external base region (layer)
305
which is also formed by local etching. Furthermore, an emitter electrode
310
is formed on the n
+
type Si emitter contact layer
307
.
During the operation of the HBT, electrons which have been implanted from the n type Si emitter layer
306
into the p type SiGe true base region (layer)
304
flow into n
+
type Si collector layer
303
through diffusion, and drift as minority carriers, thereby providing a collector current. A portion of the electrons recombine inside, or in the vicinity of, the p type SiGe true base region (layer)
304
or the p
+
type SiGe external base region (layer)
305
, thereby providing a base current. Since the size of the collector current is in proportion with the size of the base current, it is possible with this HBT to amplify an external signal by modulating the base current in accordance with the external signal.
In accordance with an HT having the above-described structure, the base layers are formed of SiGe, so that the band gaps which exist between the base layers and the emitter layer in the valence band can be Increased relative to the case where the base layers are formed of Si. As a result, the flow of holes into the emitter layer is reduced, whereby the carrier concentration in the base layers is increased and the base resistance is reduced.
In order to improve the performance of semiconductor integrated circuits in general, bipolar transistors having excellent high-speed operation characteristics are desired. Accordingly, efforts are being made to improve the high-speed operation characteristics of bipolar transistor by reducing the thickness of base layer and reducing the base-emitter parasitic capacitance or the base-collector parasitic capacitance.
For example, in order to enable a high frequency operation of the HBT having the structure as shown in FIG.
4
and provide improved high frequency characteristics, it is essential to reduce the base running time of carriers and reduce the parasitic capacitance components and resistive components. In particular, in the case where the base resistance R
B
and the base-collector capacitance C
BC
are large, a large time constant (=R
B
·C
BC
) is created, resulting in deteriorated high frequency characteristics.
In order to reduce the base-emitter parasitic capacitance or the base-collector parasitic capacitance, it is necessary to minimize the area of the base-emitter junction. However, conventional methods employing photolithography techniques cannot create a junction portion which is smaller than is possible to create given the microprocessing subtlety level achieved by photolithography techniques.
Moreover, according to conventional methods, the base layer in a base-emitter junction portion and a base extension layer (i.e., a layer which extends from the base layer to a base electrode) are generally produced by using the same crystal growing step(s). Therefore, reducing the thickness of the base layer also results in the reduction of the thickness of the base extension layer. Since this increases the electric resistance of the base extension layer, the time constant which is determined as a function of the electric resistance component of the base extension layer and the base-emitter capacitance component is also increased, thereby hindering high-speed operations. In this regard, the thickness of the base layer can only be reduced to a certain extent under the conventional methods.
In the structure illustrated in
FIG. 4
, the p
+
type SiGe external base region (layer)
305
having an enhanced p type carrier concentration is provided next to the p type SiGe true base region (layer)
304
in order to reduce the base resistance, and the base electrode
309
is formed on the p
+
type SiGe external base region (layer)
305
. However, in accordance with this structure, a base-collector capacitance is created between the p
+
type SiGe external base region (layer)
305
and the n
+
type Si collector contact layer
302
, whose capacitance value increases as the carrier concentration in the p
+
type SiGe external base region (layer)
305
is increased in order to decrease the base resistance. In other words, a trade-off relationship exists between the size of the base resistance and the size of the base-collector capacitance.
Furthermore, the high-speed operation characteristics of conventional devices are undermined due to the inter-device parasitic capacitance and the device-substrate parasitic capacitance.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a lateral bipolar transistor which includes: a substrate; a first insulative region formed on the substrate; a first semiconductor region of a first conductivity type selectively formed on the first insulative region; a second insulative region formed, so as to substantially cover the first semiconductor region; and a second semiconductor region of a second conductivity type different from the first conductivity type, a second semiconductor region being selectively formed, wherein: the second insulative region has a first opening which reaches a surface of the first semiconductor region, and the first semiconductor region has a second opening which reaches the underlying first insulative region, the second opening being provided in a position corresponding to the first opening of the second insulative region; the second semiconductor region is formed so as to fill the first opening and the second opening, thereby functioning as a base region; a lower portion of the second semiconductor region which at least fills the second opening is formed by lateral growth from a face of the first semiconductor region defining a side wall of the second opening; and the first semiconductor region includes an emitter region and a collector region formed therein.
In one embodiment of the invention, the first semiconductor region is composed essentially of monocrystalline n type Si, and the second semiconductor region is composed essentially of p type Si
x
Ge
1−x
(where 0≦x≦1).
In another embodiment of the invention, the lower portion of the second semiconductor region which at least fills the second opening has a multilayer structure at least including a first portion and a second portion, the first portion being tn contact with the face of the first semiconductor region defining the side wall of the second opening, and the second portion being in contact with the first portion.
In still another embodiment of the invention, the first portion is composed essentially of non-doped Si
y
Ge
1−y
(where 0≦y≦1), and the second portion is composed essentially of Si
x
Ge
1−x
(where 0≦x≦1) of the second conductivity type.
In still another embodiment of the invention, the first portion is composed essentially of Si of the fi
Fukuda Takeshi
Inoue Kaoru
Matsuno Toshinobu
Nishii Katsunori
Ueda Daisuke
Elms Richard
Matsushita Electronics Corporation
RatnerPrestia
Smith Brad
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