Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Forming lateral transistor structure
Reexamination Certificate
2000-05-03
2002-04-16
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Forming lateral transistor structure
C438S204000
Reexamination Certificate
active
06372595
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor processes for fabricating bipolar junction transistors, and more particularly to those processes that provide for lateral bipolar junction transistors.
2. Description of the Related Art
The fabrication of bipolar transistors is well known. Frequently, a junction-isolated process is used which is optimized for vertical NPN transistors. In many such processes, a complementary PNP transistor is available using the same process flow, but such a PNP transistor is a non-optimized “parasistic” lateral transistor which uses P-type regions (normally used for the base of the vertical NPN transistor) as the collector and emitter regions for the lateral PNP transistor.
To fabricate such a typical device, two openings are formed through an oxide layer overlying an isolated region of an epitaxial layer. A circular opening is usually formed for the emitter, and an annular opening surrounding the circular opening is usually formed for the collector. Then, a P-type base implant for the vertical device is diffused or implanted through both openings. The implanted layer (i.e., “diffusion”) formed below the circular opening is contacted and usually functions as the emitter, and the implanted layer formed below the annular opening is contacted and usually functions as the collector. The isolated region of the epitaxial layer which holds these two diffusions, and which normally forms the collector node of a vertical NPN transistor, instead is contacted to function as the base region for the lateral PNP bipolar junction transistor.
Parasitic lateral bipolar junction transistors are generally devices with poor transistor characteristics. One of the principal failings of such a transistor is its large parasitic current loss to the substrate. In critical circuits, this can cause a substantial gain-matching error between two “identical” devices when their respective collector-emitter voltages are different. The current loss is dependent upon the collector-base bias voltage, which is an undesirable voltage dependency. As such a PNP transistor is a lateral device, it usually must have its emitter and collector formed using the same P-type diffusion in order to maintain consistent alignment of the collector to the emitter (i.e., base width) around the periphery of the device.
Consequently, a simple, cost-effective semiconductor process is desired which provides improved transistor characteristics for a lateral bipolar junction transistor, such as a lateral PNP transistor, particularly in a process otherwise optimized for vertical NPN transistors.
SUMMARY OF THE INVENTION
By using a scheme that aligns multiple P-type implantations to an oxide pattern defined for certain embodiments by a single mask, multiple diffusions can be aligned to each other. Through careful selection of the collector and emitter diffusion profiles (i.e., depth and concentration), a more optimal PNP transistor may be constructed that has a collector deeper than its emitter. This scheme provides far greater collection efficiency than a traditional lateral PNP transistor made of the same diffusion for both the emitter and the collector. Greater collection efficiency provides improved Beta, better gain matching, and less parasitic loss of injected holes to the surrounding P-type junction isolation. In precision linear circuits, these characteristics are imperative.
In a broader embodiment of the present invention useful in a semiconductor fabrication process, a method for forming a lateral bipolar junction transistor includes providing a semiconductor substrate having a first polarity, forming a first dielectric layer upon the substrate, said first dielectric layer having a first and second opening therethrough, introducing a first dopant of a second polarity opposite that of the first polarity through the first opening to form a first doped layer within the semiconductor substrate there below, while substantially preventing the introduction of the first dopant through the second opening, said first doped layer corresponding to a collector region of the lateral bipolar junction transistor, and introducing a second dopant of the second polarity through the second opening to form a second doped layer within the semiconductor substrate therebelow, said second doped layer formed at a shallower depth than the first doped layer, said second doped layer corresponding to an emitter region of the lateral bipolar junction transistor.
In another embodiment of the present invention useful in a semiconductor fabrication process, a method for forming a lateral bipolar junction transistor includes providing a semiconductor substrate having a first polarity, and forming a first dielectric layer upon the substrate. The method further includes forming, using a single mask, a first and second opening through the first dielectric layer, and forming within the substrate a first implanted layer of a second polarity opposite that of the first polarity, said first implanted layer formed through and aligned to the first opening through the first dielectric layer while protecting the second opening to prevent formation of an implanted layer therethrough, said first implanted layer corresponding to a collector region of the lateral bipolar junction transistor. The method further includes forming within the substrate a second implanted layer of the second polarity having a shallower depth than the first implanted layer, said second implanted layer formed through and aligned to the second opening through the second dielectric layer, said second implanted layer corresponding to an emitter region of the lateral bipolar junction transistor.
In yet another embodiment of the present invention, a semiconductor integrated circuit structure includes a lateral bipolar junction transistor. The structure includes a semiconductor substrate of a first polarity having a top surface, and a first dielectric layer upon the top surface of the substrate, having first and second openings therethrough. The structure further includes a first doped layer at the top surface of and within the substrate, comprising a first dopant of a second polarity opposite that of the first polarity, formed below and generally aligned to the first opening within the first dielectric layer. The structure further includes a second doped layer at the top surface of and within the substrate, comprising a second dopant of the second polarity, formed below and generally aligned to the second opening within the first dielectric layer.
In still yet another embodiment of the present invention, a semiconductor integrated circuit structure includes a lateral bipolar junction transistor. The structure includes: (1) a semiconductor substrate of a first polarity having a top surface, said substrate forming the base node for the lateral bipolar junction transistor; (2) a collector region formed within the substrate and substantially aligned to a first opening through a first dielectric layer overlying the collector region, said collector region comprising a first doping profile of a second polarity opposite the first polarity; and (3) an emitter region formed within the substrate and substantially aligned to a second opening through the first dielectric layer overlying the emitter region, said emitter region comprising a second doping profile of the second polarity having a profile depth which is substantially less than that of the first doping profile.
The present invention may be better understood, and its numerous features and advantages made even more apparent to those skilled in the art by referencing the detailed description and accompanying drawings of the embodiments described below. These and other embodiments of the present invention are defined by the claims appended hereto.
REFERENCES:
patent: 4239558 (1980-12-01), Morishita et al.
patent: 4261765 (1981-04-01), Komatsu et al.
patent: 4887142 (1989-12-01), Bertotti et al.
patent: 5064773 (1991-11-01), Feist
patent: 5132235 (1992-07-01), Williams et al.
pate
Moore William E.
Thiel Frank L.
Webb Bruce
Legerity Inc.
Nhu David
Zagorin O'Brien & Graham LLP
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