Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Quality evaluation
Reexamination Certificate
2001-10-03
2003-11-11
Wachsman, Hal (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Quality evaluation
C702S035000, C702S118000, C702S083000, C700S110000, C700S121000
Reexamination Certificate
active
06647348
ABSTRACT:
FIELD
This invention relates to the manufacture of integrated circuits. More particularly, this invention relates to identifying integrated circuits that have a high probability of a latent or undetected defect.
BACKGROUND
Integrated circuits, such as semiconductor devices, are manufactured en masse on a substrate that is subsequently diced to produce the integrated circuits on individual portions of the substrate, commonly called chips or dice. Thus, a substrate, even prior to the dicing operation, typically contains many discrete integrated circuits. Prior to dicing, testing equipment is used to functionally and parametrically test the integrated circuits individually, to identify and locate defects in the integrated circuits.
However, some defects in integrated circuits are not detectible immediately. In other words, some integrated circuits contain latent defects which, although they cannot be detected early in the life cycle of the integrated circuit, tend to appear at a later point in the life cycle of the integrated circuit. Accordingly, the tester may indicate that a given integrated circuit does not have any defects, when in fact the defects are merely latent and will appear at a later point in time.
Obviously, it is counter productive to introduce such integrated circuits having latent defects into the stream of commerce. At the least it is an embarrassment to the company that produces such integrated circuits, and at the worst the integrated circuit having the latent defect fails in essential operation and puts human life at risk. Thus, tremendous energy is typically devoted to identifying and removing from the processing stream those integrated circuits that have latent defects.
One such method of identifying integrated circuits with latent defects is called burn in. Burn in is designed to detect early failures of integrated circuits by operating them for a period of time, often under stressful conditions such as elevated temperature or clock speeds above that for which they were designed, to see if they will fail during the testing period. However, burn in methods are generally undesirable for a variety of reasons, such as their expense.
There is a need, therefore, for a system for identifying integrated circuits that have latent defects.
SUMMARY
The above and other needs are provided by a method for identifying an integrated circuit having a latent defect. Test data corresponding to a set of integrated circuits is obtained, where the set of integrated circuits was processed on a single substrate. A subject integrated circuit is selected for analysis from within the set of integrated circuits. A subset of integrated circuits is identified from within the set of integrated circuits, where the subset of integrated circuits includes integrated circuits that were located in close proximity on the substrate to the subject integrated circuit. The test data for the subset of integrated circuits is analyzed to determine a defect parameter for the subset of integrated circuits. The defect parameter for the subset of integrated circuits is compared to a threshold. The subject integrated circuit is classified as having a latent defect when the defect parameter for the subset of integrated circuits violates the threshold, and the subject integrated circuit is classified as not having a latent defect when the defect parameter for the subset of integrated circuits does not violate the threshold.
In this manner, integrated circuits having a likelihood of latent defects are identified without performing a difficult and costly burn in procedure. However, the defect parameter can also be used in other ways. For example, integrated circuits associated with a defect parameter that violates a given value can be selected for, in alternate embodiments, a longer than normal burn in, a shorter than normal burn in, or no burn in at all. Further, the classification for the subject integrated circuit is not based merely on whether the subset of other integrated circuits in close proximity to the subject integrated circuit passed or failed all of their functional and parametric testing. Rather, the classification is based on a defect parameter that is determined from an analysis of the test data for the subset of other integrated circuits. Thus, there is provided a more substantial basis for the classification than merely determining if integrated circuits near the subject integrated circuit are binned as failures.
In a most preferred embodiment the defect parameter comprises an average number of defects for the subset of integrated circuits. The test data for the set of integrated circuits preferable includes defect data for functional tests and parametric tests. Most preferably the method is performed for subject integrated circuits for which the test data indicates no defects. The threshold is preferably violated when the defect parameter is equal to or greater than the threshold. In one embodiment the threshold is a predetermined value, and in an alternate embodiment the method includes the additional step of calculating the threshold based at least in part on the test data for the subset of integrated circuits. Further, the threshold in one embodiment changes based on conditions such as the intended customer for the subject integrated circuit, or on the stability of the process used to manufacture the subject integrated circuit.
Most preferably the subset of integrated circuits includes the eight nearest neighbor integrated circuits to the subject integrated circuit. The test data is preferably obtained for the set of integrated circuits from a tester before the substrate on which the set of integrated circuits were processed is diced. The analysis steps are preferably performed off tester. However, some steps of the method, such as the step of classifying the subject integrated circuit as either having or not having a latent defect, can be performed after the substrate has been diced, and even after the subject integrated circuit has been packaged if substrate identification and location information in regard to the subject integrated circuit has been kept.
REFERENCES:
patent: 5986950 (1999-11-01), Joseph
patent: 5991699 (1999-11-01), Kulkarni et al.
patent: 6300771 (2001-10-01), Goshima
LSI Logic Corporation
Luedeka Neely & Graham P.C.
Wachsman Hal
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