Latency tolerant risc-based multiple processor with event driven

Details Latency tolerant risc-based multiple processor with event driven Latency tolerant risc-based multiple processor with event driven

1991-12-04

1995-08-15

Kriess, K.

Boots, shoes, and leggings

364DIG1, 364229, 36423223, 364260, 3642602, 364280, 3642813, 3642817, 364284, 395650, G06F 1300

Patent

active

054427975

ABSTRACT:
A method and an apparatus for reconciling communication and locality by enabling a user/programmer to write programs in an extended procedural language which explicitly manipulate locality. The multiprocessor includes a plurality of processing elements connected to each other each processing element having a unique address and including a central processing unit for executing local CPU code and reading and writing local data and a locality manager for controlling data movement between processing elements which are cooperating on a single task by executing local locality manager code which indicates when shared data can be released and when non-local data is requested.

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