Latency tolerant pipeline synchronization

Details Latency tolerant pipeline synchronization Latency tolerant pipeline synchronization

2006-10-30

2009-11-17

Treat, William M (Department: 2181)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

C712S200000, C712S228000

Reexamination Certificate

active

07620798

ABSTRACT:
A synchronization mechanism is used to synchronize events across multiple execution pipelines that process transaction streams. A common set of state configuration is included in each transaction stream to control processing of data that is distributed between the different transaction streams. Portions of the state configuration correspond to portions of the data. Execution of the transaction streams is synchronized to ensure that each portion of the data is processed using the state configuration that corresponds to that portion of the data. The synchronization mechanism may be used for multiple synchronizations and when the synchronization signals are pipelined to meet chip-level timing requirements.

REFERENCES:
patent: 5428756 (1995-06-01), Edamatsu et al.
patent: 6272621 (2001-08-01), Key et al.
patent: 2003/0063092 (2003-04-01), Margittai et al.

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