Latency signal generating circuit and semconductor device...

Details Latency signal generating circuit and semconductor device... Latency signal generating circuit and semconductor device...

2009-06-17

2011-10-04

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S161000, C327S164000, C365S194000

Reexamination Certificate

active

08030981

ABSTRACT:
A semiconductor device includes a latency signal generating circuit for generating a latency signal corresponding CAS latency by measuring a delay amount reflected at a delay locked loop and reflecting the measured delay amount at a read command signal, and a delay locked loop for controlling an internal clock signal applied to the latency signal generating circuit corresponding to the read command and the latency signal. The semiconductor device includes an internal clock signal generating block configured to generate an internal clock signal, a latency generating block configured to generate a latency signal by synchronizing a read command signal with the internal clock signal at a time corresponding to a CAS latency value and a measured delay value, and an input controlling block configured to activate the reference clock signal using an external clock signal in response to the read command signal and the latency signal.

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patent: 6509776 (2003-01-01), Kobayashi et al.
patent: 7038972 (2006-05-01), Seo et al.
patent: 7170819 (2007-01-01), Szczypinski
patent: 2008/0192563 (2008-08-01), Cho
patent: 2009/0040847 (2009-02-01), Lee
patent: 2009/0116313 (2009-05-01), Jang
patent: 1020050074247 (2005-07-01), None
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patent: 100931026 (2009-12-01), None
Notice of Allowance issued from Korean Intellectual Property Office on Aug. 31, 2010.

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