Latency error detection circuit for a measurement system

Details Latency error detection circuit for a measurement system Latency error detection circuit for a measurement system

1994-05-24

1996-07-02

Beausoliel, Jr., Robert W.

Excavating

371 61, 3642608, 364DIG1, G06F 1100

Patent

active

055330371

ABSTRACT:
A latency error detection circuit including two cascaded latches receiving a clock signal from a measuring system upon the occurrence of an event and correspondingly asserting a bit to a processing system, and a circuit for clearing the first latch after the processing system acknowledges detecting the bit being asserted. If the second latch is clocked before the first latch is cleared, the second latch sets an error bit indicating a latency error condition. The processor system monitors the error bit to determine whether a latency error has occurred.

REFERENCES:
patent: 3701096 (1972-10-01), Hunter et al.
patent: 3805040 (1974-04-01), Boden et al.
patent: 4763296 (1988-08-01), Gerakei
patent: 4918696 (1990-04-01), Pordham et al.
patent: 4972414 (1990-11-01), Borkenhagen et al.
patent: 5228129 (1993-07-01), Bryant et al.

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