Latency-based scheduling of instructions in a superscalar proces

Details Latency-based scheduling of instructions in a superscalar proces Latency-based scheduling of instructions in a superscalar proces

1996-11-19

1998-09-01

Donaghue, Larry D.

395393, 395391, G06F 934

Patent

active

058023860

ABSTRACT:
Instructions are efficiently scheduled for execution based on a stored identification of the first processor cycle when a result of a previous instruction required as an operand for the instruction to be scheduled will become available. Examination of stored processor cycle identifications for the operands of an instruction reveals the earliest processor cycle when the instruction may be executed. By selecting the greater of the largest stored processor cycle identification for an operand of the instruction and the earliest available processor cycle for an execution unit required to execute the instruction, the instruction is efficiently scheduled for the earliest possible execution. Latency of previous instructions in generating an operand of the instruction being scheduled is automatically accommodated.

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