Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Patent
1996-11-07
1999-07-06
Hardy, David B.
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
257520, 257501, 257347, H01L 2902
Patent
active
059201088
ABSTRACT:
Trenches 72 are formed in substrate 17 late in the fabrication process. In order to avoid trench sidewall stresses that cause defects in the substrate monocrystalline lattice, the trenches are filled after a final thick thermal oxide layer, such as a LOCOS layer 25, is grown. The trenches 72 are also filled after a final deep diffusion, i.e. a diffusion in excess of one micron.
REFERENCES:
patent: 4140558 (1979-02-01), Murphy et al.
patent: 4631803 (1986-12-01), Hunter et al.
patent: 4884117 (1989-11-01), Neppl et al.
patent: 4987471 (1991-01-01), Easter et al.
patent: 5027184 (1991-06-01), Soclof
patent: 5100830 (1992-03-01), Morita
patent: 5135883 (1992-08-01), Bae et al.
patent: 5173436 (1992-12-01), Gill et al.
patent: 5200348 (1993-04-01), Uchida et al.
patent: 5217919 (1993-06-01), Gaul et al.
patent: 5241211 (1993-08-01), Tashiko
patent: 5315144 (1994-05-01), Cherne
patent: 5434446 (1995-07-01), HIlton et al.
patent: 5668397 (1997-09-01), Davis et al.
Hemmenway Donald Frank
Pearce Lawrence George
Hardy David B.
Harris Corporation
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