Latching zero-power sense amplifier with cascode

Details Latching zero-power sense amplifier with cascode Latching zero-power sense amplifier with cascode

1993-09-08

1995-04-25

Sikes, William L.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327170, 327 7, 327 78, 327 72, H03K 512, H03K 5153, G01R 1900

Patent

active

054102685

ABSTRACT:
A zero-power sense amplifier for implementing a wide or multiple input NOR gate for receiving a product term of a group of array cells in a programmable logic device (PLD). In a sleep mode, or low power mode, the zero-power sense amplifier latches its previous state while drawing negligible power rather than returning to one particular state, such as a low state, as in previous devices, enabling recovery time to be reduced after entering an awake mode. The zero power sense amplifier further reduces recovery time upon powering up from a sleep mode by maintaining the product term voltage close to a threshold input voltage during sleep mode while still drawing negligible power.

REFERENCES:
patent: 5189322 (1993-02-01), Chan et al.
patent: 5272670 (1993-12-01), Hashimoto
patent: 5291080 (1994-03-01), Amagasaki
U.S. patent application Ser. No. 08/034,537, "Cascode Array Cell Partitioning For A Sense Amplifier Of A Programmable Logic Device", Filed. Mar. 19, 1993.
U.S. patent application Ser. No. 07/754,920, "Dual Port Memory, Such As Used In Color Lookup Tables For Video Systems", Filed Sep. 4, 1991.

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