Latching wordline driver for multi-bank memory

Details Latching wordline driver for multi-bank memory Latching wordline driver for multi-bank memory

1999-01-11

2000-10-10

Nelms, David

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

365195, G11C 800

Patent

active

061308552

ABSTRACT:
A memory device is described which includes latching wordline driver circuits. The wordline driver circuits include a latch responsive to phase lines of an address tree decode configuration. The latch has been described as a single latching transistor which allows transitions in shared row address lines while maintaining an active wordline signal. The latching wordline driver is particularly useful in multi-bank memory devices where row address lines are shared between the memory banks.

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