Latching wordline driver for multi-bank memory

Details Latching wordline driver for multi-bank memory Latching wordline driver for multi-bank memory

1999-06-14

2000-04-04

Nelms, David

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523003, G11C 800

Patent

active

060469587

ABSTRACT:
A memory device is described which includes latching wordline driver circuits. The wordline driver circuits include a latch responsive to phase lines of an address tree decode configuration. The latch has been described as a single latching transistor which allows transitions in shared row address lines while maintaining an active wordline signal. The latching wordline driver is particularly useful in multi-bank memory devices where row address lines are shared between the memory banks.

REFERENCES:
patent: 4703453 (1987-10-01), Shinoda et al.
patent: 5687132 (1997-11-01), Rao
patent: 5754838 (1998-05-01), Shibata et al.
patent: 5798978 (1998-08-01), Yoo et al.
Descriptive literature entitled,"400MHz SLDRAM, 4Mx16 SLDRAM Pipelined, Eight Bank, 2.5 V Operation," SLDRAM Consortium Advance Sheet, published throughout the United States, pp. 1-22.
"Draft Standard for a High-Speed Memory Interface (SyncLink)," Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, Copyright 1996 by the Institute of Electrical and Electronics Engineers, Inc. New York, NY, pp. 1-56.

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