Latching serial data in an ink jet print head

Details Latching serial data in an ink jet print head Latching serial data in an ink jet print head

2001-02-09

2003-04-15

Barlow, John (Department: 2853)

Incremental printing of symbolic information

Ink jet

Controller

C347S237000, C347S247000, C347S211000, C347S168000

Reexamination Certificate

active

06547356

ABSTRACT:

FIELD OF THE INVENTION
The present invention is generally directed to ink jet print heads. More particularly, the invention is directed to a circuit for transferring serial print data onto a data bus in a print head chip.
BACKGROUND OF THE INVENTION
The manufacturing costs of ink jet print heads and print head cartridges is significantly affected by the number of signal lines that must pass from the print head chip to the TAB circuit on which the chip is mounted on the print head cartridge, and front the print head cartridge to the printer. Besides cost, high frequency clock and data input/output (I/O) lines tend to introduce electromagnetic interference which must be accounted for in the design of cabling that connects the printer and the print head cartridge. Thus, ways to reduce the number of clock and I/O signal lines between the chip and TAB circuit, and between the printer and the print head cartridge, are constantly being sought by print head designers.
SUMMARY OF THE INVENTION
The present invention addresses the above needs by providing a print data loading circuit for receiving at least N bits of serial data on a serial input data line, where at least some of the serial data describes an image to be formed on a print medium by a printing device. The loading circuit provides the data to a data bus in an addressing circuit for addressing one or more image-forming elements in the printing device. The loading circuit includes a serial shift register having N number of single-bit storage registers, including a first single-bit storage register, an Nth single-bit storage register, and N−2 number of single-bit storage registers serially coupled between the first and Nth single-bit storage registers. The first storage register has a first-register data output, a first-register data input coupled to the serial input data line, and a first-register clock input coupled to a clock line. The Nth storage register has an Nth-register data input, an Nth-register data output, and an Nth-register clock input coupled to the clock line. The data loading circuit also includes N−1 number of data latches, each having a data-latch input, a data-latch output, and a data-latch clock input. The data-latch inputs of the data latches are coupled to the data outputs of the first single-bit storage register and the N−2 number of single-bit storage registers serially coupled between the first and Nth single-bit storage registers. The data-latch outputs are coupled to the N−1 number of selection lines that are coupled to the data bus. The data-latch clock inputs of the data latches are coupled to the Nth-register data output.
Based on this configuration, a data bit transferred from the Nth-register data output to the data-latch clock inputs acts as a load trigger bit to cause at least some of the other data bits in the other single-bit storage registers to be loaded into the N−1 number of data latches. By providing the trigger bit from the Nth register of the shift register, the present invention eliminates the need for a second clock input to latch the print data into the data latches. Eliminating a second clock input reduces print head costs and potential EMI problems.
In another aspect, the invention provides a method for sending print data to an ink droplet generator addressing circuit in an ink jet print head. The method includes shifting N−1 of N number of bits of serial input data into an N-bit serial shift register, where a first bit of the N number of bits is a load trigger bit. The method also includes shifting an Nth bit of the N number of bits into the shift register at a first time, thereby causing the load trigger bit to be shifted into an Nth register of the shift register. At a second time, the load trigger bit is provided from the Nth register of the shift register to clock inputs of N−1 number of data latches. The N−1 number of data latches are then loaded with the N−1 number of bits of data residing in the shift register when the load trigger bit is provided to the clock inputs of the data latches. The method further includes providing the N−1 number of bits of data from the N−1 number of data latches to the ink droplet generator addressing circuit.


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