Latching sense amplifier with tri-state output

Details Latching sense amplifier with tri-state output Latching sense amplifier with tri-state output

2002-09-27

2003-11-04

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S057000

Reexamination Certificate

active

06642749

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to sense amplifiers for semiconductor integrated circuit memories and, more particularly, to a latching sense amplifier having a tri-state output.
Semiconductor integrated circuit memories include a plurality of memory elements or cells, which are arranged in rows and columns. The memory cells in each column are coupled to a respective pair of complementary bit lines. Each pair of bit lines has a differential voltage representing the data being read from or written to a memory cell in that column.
A typical memory I/O buffer includes a column multiplexer, a sense amplifier and a write driver. The column multiplexer multiplexes groups of bit lines into respective data input-output lines. There is a sense amplifier and a write driver for each pair of multiplexed data input-output lines.
In some applications, the sense amplifiers have tri-state output stages that allow the outputs of a group of sense amplifiers to be coupled together to a single “wired-OR” node. This wired-OR node can then be coupled to a data output buffer or latch. In these applications, the column multiplexing function can be combined with the enable signals provided to the sense amplifiers such that only one sense amplifier in the group is enabled at one time.
Existing sense amplifiers having tri-state outputs have several disadvantages. For example, sense amplifiers having outputs that are driven by tri-state inverters typically use stacked MOS devices in the output driver, which reduce the drive strength of the output driver by half. In order to increase the drive strength, the MOS devices are formed larger and therefore consume more area on the integrated circuit. Also, larger MOS devices add more capacitive load to the outputs, causing the sense amplifier to become slower. In addition, the timing of the output transition when reading a high value and when reading a low value may not be balanced, so the overall delay from when the enable signal becomes active to a transition on the data output is long.
In another example, both latch outputs are used to drive respective pull-up and pull-down transistors in an output stage. While this type of circuit can have faster output switching and greater drive strength, the output cannot be used directly in a wired-OR implementation since voltage levels within unselected sense amplifiers can leak through the output driver and disrupt the wired-OR node.
Improved tri-state latching sense amplifiers are desired which have fast output switching and consume a relatively small area when fabricated.
SUMMARY OF THE INVENTION
One embodiment of the present invention is directed to a tri-state sense amplifier, which includes an enable input, a latch and an output driver. The latch has first and second complementary inputs and first and second complementary latch outputs, which are gated by the enable input. The output driver includes a data output, a pull-up transistor coupled to the data output and having a control terminal coupled to the first latch output, and a pull-down transistor coupled to the data output and having a control terminal coupled to the second latch output.
Another embodiment of the present invention is directed to a tri-state sense amplifier, which includes an enable input, a latch and an output driver. The latch includes first and second complementary inputs and first and second complementary latch outputs. The output driver includes a data output, a pull-up transistor coupled to the data output and having a control terminal driven by the first latch output, and a pull-down transistor coupled to the data output and having a control terminal driven by the second latch output. A first logic gate is coupled between the first latch output and the control terminal of the pull-up transistor and gates the first latch output with the enable input. A second logic gate is coupled between the second latch output and the control terminal of the pull-down transistor and gates the second latch output with the enable input.
Yet another embodiment of the present invention is directed to a tri-state sense amplifier, which includes an enable input, a latch, a logic circuit and an output driver. The latch has first and second complementary inputs and first and second complementary latch outputs. The logic circuit gates the first and second latch outputs with the enable input to produce first and second complementary gated outputs, respectively. The output driver produces a data output based on the first and second complementary gated outputs, wherein the data output has either a logic high state, a logic low state or a high impedance state.


REFERENCES:
patent: 5546537 (1996-08-01), McClure
patent: 5563835 (1996-10-01), Oldham
patent: 5764086 (1998-06-01), Nagamatsu et al.
patent: 6268747 (2001-07-01), Barnes
patent: 6307400 (2001-10-01), Kim et al.
patent: 6459299 (2002-10-01), Hirano et al.

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