Latching inputs and enabling outputs on bidirectional pins with

Details Latching inputs and enabling outputs on bidirectional pins with Latching inputs and enabling outputs on bidirectional pins with

1996-08-20

1998-06-09

Chin, Stephen

Pulse or digital communications

Miscellaneous

375376, 395832, 331DIG2, 326136, G06F 1300

Patent

active

057647143

ABSTRACT:
A circuit for latching inputs and enabling outputs on a bidirectional pin using a PLL lock detect circuit is disclosed. A PLL lock detect circuit generates an active lock control signal when an output reference signal is phase locked relative to an input reference signal applied to a phase locked loop (PLL) circuit. A latch and enable circuit is responsive to this lock control signal to latch the input signal (off of the pin), and, thereafter, enable output of an output signal onto the bidirectional pin. The latch and enable circuit includes a data latch to store the input signal when the lock control signal goes to an active state. The latch and enable circuit also includes a delay circuit to delay the lock control signal to produce a delayed lock control signal, and a tristateable output driver that is tristated when the delayed lock control signal is inactive, but, operates to pass (i.e., enable) the output signal to the bidirectional pin when the delayed lock control signal is active.

REFERENCES:
patent: 5008635 (1991-04-01), Hanke et al.
patent: 5539338 (1996-07-01), Moreland
patent: 5615390 (1997-03-01), Kurahara
Shariatdoust et al. (AT&T Bell Laboratories), IEEE 1992 Custom Integrated Circuits Conference, pp. 24.2.1-24.2.5.
Alvarez et al., 1994 Symposium on VLSI Circuits Digest of Technical Papers, pp. 37-38.
Preliminary Data Sheet for Part CY2291, High Performance Data Handbook, Cypress Semiconductor, Pub. May 1995, pp. 10-13 to 10-17.

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