Latching input buffer for an ATD memory

Details Latching input buffer for an ATD memory Latching input buffer for an ATD memory

1990-04-23

1991-03-26

Clawson, Jr., Joseph E.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518905, 365202, 3652335, 307279, G11C 1141

Patent

active

050035134

ABSTRACT:
An ATD memory has an input buffer which latches addresses while maintaining good D.C. margin, hysteresis, and transition detection. The input buffer includes two input circuits for receiving the address. A transmission-gate type latch is used to latch the outputs of the two input circuits. An internal buffer circuit receives the output of the latch and provides internal address signals useful to a decoder in selecting a memory cell. The internal buffer circuit also provides slow and fast signals useful in performing transition detection. The latch either provides outputs responsive to the address signal or an output representative of the address signal at the time a latch enable signal is received.

REFERENCES:
patent: 4707809 (1987-11-01), Ando
patent: 4712197 (1987-12-01), Sodo
patent: 4716550 (1987-12-01), Flannagan et al.
patent: 4843596 (1989-06-01), Miyatake et al.
patent: 4852063 (1989-07-01), McNutt
patent: 4912679 (1990-03-01), Shinoda et al.
patent: 4939692 (1990-07-01), Kendall
patent: 4943962 (1990-07-01), Imamiya et al.

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