Latching comparator utilizing resonant tunneling diodes and...

Details Latching comparator utilizing resonant tunneling diodes and... Latching comparator utilizing resonant tunneling diodes and...

1999-08-13

2001-06-26

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S077000, C327S195000

Reexamination Certificate

active

06252430

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to converting analog information to digital information. More particularly, the present invention relates to a high frequency latching comparator for analog to digital conversion.
BACKGROUND
Analog to digital conversions are often implemented using quantizers that sample the input analog signal at a selected sampling frequency (f
S
), make a determination whether the input analog signal is higher or lower than a reference signal, and output a high or low voltage depending upon this determination. The reference signal may be a DC or AC voltage. Quantizers for analog to digital conversions with high frequency input signals and sampling frequencies above 1 GHz must be capable of making decisions quickly and reliably. These high sampling and input frequencies, however, create significant problems in achieving the goal of consistent and correct operation of such circuits.
A prior quantizer implementation to achieve high frequency analog to digital conversion is the latching comparator
100
depicted in
FIG. 1
(Prior Art). This prior latching comparator
100
includes a preamplifier portion, including transistors
116
and
122
, and a latch portion, including transistors
118
and
120
. The preamplifier and latch portions are clocked out of phase using the track signal (TRACK)
130
and the latch signal (LATCH)
132
. Mode selection circuitry, which includes tracking control circuitry that receives the track signal (TRACK)
130
and latching control circuitry that receives the latch signal (LATCH)
132
, determines whether the latching comparator is in a tracking or latching mode. While illustrated as npn bipolar devices, the transistors
118
and
120
could also be pnp bipolar transistors or field effect transistors (FETs).
Looking at the preamplifier portion of this circuitry in more detail, an input signal (V
IN
)
106
is applied to bias transistor
116
. A reference voltage (V
REF
)
124
is connected to bias transistor
122
. Resistors
112
and
114
are connected between ground
102
and the collectors of transistors
116
and
122
, respectively. The emitters of transistors
116
and
122
are connected together at internal track node
142
. Transistor
126
, which is the tracking control circuitry, is connected between internal track node
142
and node
140
and has a bias voltage set by the track signal (TRACK)
130
. Transistor
136
is connected between node
140
and resistor
138
and has a constant bias voltage set by bias voltage (V
BB
)
134
. Resistor
138
is connected between the emitter of transistor
136
and the negative supply voltage (V
EE
)
104
. The transistor
136
and the resistor
138
act as a current source in operation.
Looking at the latch portion of this circuitry in more detail, transistor
128
is connected between node
140
and internal latch node
144
. Transistor
128
, which is the latching control circuitry, is biased by a latch signal (LATCH)
132
. Transistors
118
and
120
are connected with the collector of transistor
118
being connected to the base of transistor
120
, the collector of transistor
120
being connected to the base of transistor
118
, and the emitters of transistors
118
and
120
being connected together to form internal latch node
144
. The output (V
OUT2
)
110
is taken from the collectors of transistors
120
and
122
, which are connected together. The output (V
OUT1
)
108
is taken from the collectors of transistors
118
and
116
, which are connected together.
In operation, when the track signal (TRACK)
130
is high and the latch signal (LATCH)
132
is disabled (LATCH=low), the differential preamplifier portion of the circuitry is enabled. In this tracking mode, the differential output voltage of node (V
OU2
)
110
minus node (V
OUT1
)
108
tracks the input signal (V
IN
)
106
. When the latch signal (LATCH)
132
goes high and the preamplifier stage is disabled (TRACK=low), the latching portion of the circuitry is enabled. At that point, the differential output voltage of node (V
OUT2
)
110
minus node (V
OUT1
)
108
will be either high or low. In this latching mode, the cross-coupled latch provided by transistors
118
and
120
establishes a positive feedback loop that amplifies the differential preamplifier output to provide a low or high indication of the input signal (V
IN
)
106
. The track signal (TRACK)
130
transitions from high to low and back at the desired sampling frequency (f
S
). The latch signal (LATCH) is set to be 180 degrees out of phase with respect to the track signal (TRACK)
130
. Significantly and disadvantageously, the speed of the resulting latching comparator
100
is limited by the unity current gain frequency (f
T
) of the transistors
118
and
120
.
This prior latching comparator circuit has various disadvantages including operational problems at high speeds and low input voltages. Thus, it is desirable to improve the performance of this prior latching comparator circuit.
SUMMARY OF THE INVENTION
In accordance with the present invention, a latching comparator and associated method are disclosed that utilize resonant tunneling diodes, or other two-terminal devices possessing regions of negative differential operating resistance in their current-voltage characteristics, and Schottky diodes to provide high speed and reliable analog to digital conversions.
In one embodiment, the present invention is a latching comparator including a differential amplifier, first and second two-terminal devices having negative differential operating resistances, and first and second cross-coupled resistors. The differential amplifier has an analog signal and a reference signal as inputs, has a first and second output nodes, and has an internal track node. The first two-terminal device is connected between the first output node and a first internal node. The second two-terminal device is connected between the second output node and a second internal node. The first cross-coupled resistor is connected between the second output node and the first internal node. And the second cross-coupled resistor is connected between the first output node and the second internal node. In addition, the first and the second internal nodes comprise an internal latch node. In more detailed embodiments, the first and second two terminal devices are tunnel diodes or resonant tunneling diodes. The first and second cross coupled resistors comprise a plurality of serially connected resonant tunneling diodes. The reference signal is a DC signal. And the differential amplifier includes two transistors differentially connected.
In a further embodiment, the latching comparator includes mode selection circuitry coupled to the internal track node and the internal latch node and having a track mode signal and a latch mode signal as inputs, respectively. The mode selection circuitry may include a first transistor having the track mode signal as a control voltage and may include a second transistor and a third transistor both having the latch mode signal as a control voltage. In addition, the first, second and third transistors may be hetero-junction bipolar transistors. Also, the latch mode signal may match the track mode signal except for being offset in phase from the track mode signal by 180 degrees. And the input signal and the track mode signal may both have frequencies above 1 GHz.
In still a further embodiment, the latching comparator may include a first Schottky diode connected in series with the first two-terminal device between the first output node and the first internal node, a second Schottky diode connected in series with the second two-terminal device between the second output node and the second internal node, a third Schottky diode connected in series with the first cross-coupled resistor between the second output node and the first internal node, and a fourth Schottky diode connected in series with the second cross-coupled resistor between the first output node and the second internal node.
In another respect, the prese

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