Latching comparator employing transfer gates

Details Latching comparator employing transfer gates Latching comparator employing transfer gates

1991-04-09

1993-03-23

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072721, 307571, 307355, 307356, H03K 326, H03K 3284

Patent

active

051967375

ABSTRACT:
First and second outputs of a differential amplifier stage are coupled via first and second selectively enabled transmission gates to first and second inputs of a selectively enabled complementary flip-flop. During a data sensing and acquisition phase, the transmission gates are enabled and the flip-flop is disabled. Although the flip-flop is disabled, two of its cross coupled transistors are coupled via the transmission gates to the differential amplifier stage. This enhances the setting of the flip-flop when it is subsequently enabled and the transmission gates are disabled.

REFERENCES:
patent: 4511810 (1985-04-01), Yukawa
patent: 4716312 (1987-12-01), Mead et al.
patent: 4939384 (1990-07-01), Shikata et al.
patent: 4985905 (1991-01-01), Kubinec

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