Latching circuit speed-up technique

Details Latching circuit speed-up technique Latching circuit speed-up technique

1983-06-30

1986-01-14

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 307291, 307591, G11C 506

Patent

active

045647720

ABSTRACT:
A latching circuit with reduced signal delay is disclosed comprising a latch and an output logic function circuit. The same signals are applied to the output gate of the latch and to the logic function circuit, whereby the output gate and the logic function circuit effectively are connected in parallel, rather than in series, to eliminate one level of logic delay. An additional logic signal is applied only to the logic function circuit but not to the latch. Provision can be made for applying inverted data to the latch in the event that the latch and the logic function circuit are implemented with NAND or NOR gates.

REFERENCES:
patent: 2942192 (1960-06-01), Lewis
patent: 3154744 (1964-10-01), Maley
patent: 3467839 (1969-09-01), Miller
patent: 3530384 (1968-07-01), Zussman
patent: 3679915 (1972-07-01), Kriger
patent: 3723760 (1973-03-01), Ebrahimi
patent: 3740590 (1973-06-01), Hart et al.
patent: 3783254 (1974-01-01), Eichelberger
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patent: 4019144 (1977-04-01), Lincoln et al.
patent: 4078204 (1978-03-01), Gauthier
patent: 4085341 (1978-04-01), Reinert
patent: 4314166 (1982-02-01), Bismarck
patent: 4315167 (1982-02-01), Pelc
patent: 4439690 (1984-03-01), Maley et al.
"Manual of Logic Circuits", G. A. Maley, Prentice Hall, 1970, p. 78.
IBM TDB, vol. 5, No. 11, Apr. 1963, "Gating Network for Oscillators", G. A. Maley & R. W. Miller, pp. 101-102.

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