Latched fedback memory finite-state-engine

Details Latched fedback memory finite-state-engine Latched fedback memory finite-state-engine

1987-02-24

1988-11-22

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 3072721, 377 64, H03K 3027

Patent

active

047868295

ABSTRACT:
Disclosed herein is a simple latched-fedback-memory finite-state-engine that produces an inherently stable output upon the receipt of a clock signal, that is synchronously or asynchronously generated. The finite-state-engine comprises at least three latches and a function module, wherein the output of one latch is used as an input for the function module and a previous output of the function module is re-entered as an input into the function module.

REFERENCES:
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patent: 4357678 (1982-11-01), Davis
patent: 4366393 (1982-12-01), Kasuya
patent: 4488229 (1984-12-01), Harrison
patent: 4562427 (1985-12-01), Ecton
patent: 4706217 (1987-11-01), Shimizu et al.
Pilost et al, "Latched Inputs--An Improvement to PLA", IBM T.D.B., vol. 20, No. 11A, Apr. 1978, pp. 4438-4439.
Mead and Conway, Introduction to VLSI Systems, Addison-Wesley Pub. Co., Reading, Mass., Oct. 1980, pp. 82-85.

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