Latched DRAM write bus for quickly clearing DRAM array with mini

Details Latched DRAM write bus for quickly clearing DRAM array with mini Latched DRAM write bus for quickly clearing DRAM array with mini

1997-01-13

1998-07-21

Nelms, David C.

Static information storage and retrieval

Powering

Conservation of power

36518905, 36523006, G11C 700

Patent

active

057843295

ABSTRACT:
The power consumed by repetitive switching and precharging of a DRAM bus during repetitive write cycles is reduced by latching the data lines to the DRAM array during repeated data writes in a way which avoids the necessity of precharging the lines before every write. A fast write mode is invoked when repeated writes are to occur and is cleared at the end of the repeated writes.

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