Latched decoder for digit outputs to an electronic digital calcu

Details Latched decoder for digit outputs to an electronic digital calcu Latched decoder for digit outputs to an electronic digital calcu

1974-11-26

1976-04-27

Gruber, Felix D.

Registers

Transfer mechanism

Traveling pawl

3401725, G06F 1502, G06F 314

Patent

active

039537196

ABSTRACT:
A greatly simplified calculator circuit implemented, for example, utilizing I.sup.2 L technology, is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator is a latched decoder for multiplexed digit outputs to the display. The latched decoder reduces the circuitry ordinarily utilized to provide the digit outputs to permit fabrication on the smaller chip. The digit outputs are selected one or more at a time by a load output instruction. A selected number of bits of the load output instruction selects the digit.

REFERENCES:
patent: 3364471 (1968-01-01), Bienhoff et al.
patent: 3760171 (1973-09-01), Wang et al.
patent: 3781852 (1973-12-01), White et al.
patent: 3812489 (1974-05-01), Hirano et al.
patent: 3858197 (1974-12-01), Shimizu et al.

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